公开(公告)号：US07355250B2

公开(公告)日：2008-04-08

申请号：US11222707

申请日：2005-09-08

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

IPC: H01L23/62 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/0262

Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.

Abstract translation: 提供具有寄生可控硅整流器（SCR）结构和可控保持电流的静电放电（ESD）器件。 在第一N +掺杂区域和第一P +掺杂区域之间保持第一距离，并且在第二P +掺杂区域和第三N +掺杂区域之间保持第二距离。 此外，通过调制第一距离和第二距离，可以将ESD装置的保持电流设定为特定值。 保持电流与第一距离和第二距离成反比。

公开(公告)号：US20070004150A1

公开(公告)日：2007-01-04

申请号：US11427773

申请日：2006-06-29

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

IPC: H01L21/8234 ,  H01L23/62

CPC classification number: H01L27/0259

Abstract: An electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided. The semiconductor structure has multi-stage protection semiconductor circuit finction and adjustable discharge capacity. The single-trigger or multi-trigger semiconductor structure may be fabricated by using the conventional semiconductor process, and can be applied to IC semiconductor design and to effectively protect the important semiconductor devices and to prevent the semiconductor devices from ESD damage. In particular, the present invention can meet the requirements of high power semiconductor device and has better protection function compared to conventional ESD protection circuit. In the present invention, a plurality of N-wells or P-wells connected in parallel are used to adjust the discharge capacity of various wells in the P-substrate so as to improve the ESD protection capability and meet different power standards.

Abstract translation: 提供具有可调单触发或多触发电压的静电放电（ESD）保护装置。 半导体结构具有多级保护半导体电路的功能和可调放电容量。 单触发或多触发半导体结构可以通过使用传统的半导体工艺制造，并且可以应用于IC半导体设计并且有效地保护重要的半导体器件并且防止半导体器件受到ESD损坏。 特别地，本发明可以满足大功率半导体器件的要求，与传统的ESD保护电路相比具有更好的保护功能。 在本发明中，使用并联连接的多个N阱或P阱来调整P基板中的各个阱的放电容量，以提高ESD保护能力并满足不同的功率标准。

公开(公告)号：US06903421B1

公开(公告)日：2005-06-07

申请号：US10758919

申请日：2004-01-16

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

IPC: H01L23/62 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/0634 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/7816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The isolated high-voltage LDMOS transistor according to the present invention includes a split N-well and P-well in the extended drain region. The P-well is split in the extended drain region of the N-well to form a split junction-field in the N-well. The split N-well and P-well deplete the drift region, which shifts the electric field maximum into the bulk of the N-well. This achieves a higher breakdown voltage and allows the N-well to have a higher doping density. Furthermore, the LDMOS transistor according to the present invention includes a N-well embedded beneath the source diffusion region. This creates a low-impedance path for the source region, which restricts the transistor current flow between the drain region and the source region.

Abstract translation: 根据本发明的隔离的高电压LDMOS晶体管在扩展漏极区域中包括分裂的N阱和P阱。 P阱在N阱的扩展漏极区域中分裂，以在N阱中形成分离的连接场。 分裂的N阱和P阱消耗了漂移区域，其将电场最大值移动到N阱的大部分中。 这实现了更高的击穿电压并且允许N阱具有更高的掺杂密度。 此外，根据本发明的LDMOS晶体管包括嵌入在源极扩散区之下的N阱。 这为源极区域产生低阻抗路径，这限制了漏极区域和源极区域之间的晶体管电流。

公开(公告)号：US08772854B2

公开(公告)日：2014-07-08

申请号：US13437503

申请日：2012-04-02

Applicant: Ching-Hung Fu ,  Chun-Yao Ko ,  Tuo-Hsin Chien ,  Ting-Chen Hsu

Inventor： Ching-Hung Fu ,  Chun-Yao Ko ,  Tuo-Hsin Chien ,  Ting-Chen Hsu

IPC: H01L29/788 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L21/0223 ,  H01L21/265 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32055 ,  H01L21/76205 ,  H01L21/76213 ,  H01L21/76224 ,  H01L21/76237 ,  H01L27/11517 ,  H01L27/11558 ,  H01L28/40 ,  H01L28/60 ,  H01L29/42324 ,  H01L29/66825

Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.

Abstract translation: 器件包括有源区和耦合电容。 电容器包括作为耦合电容器的上电容器板的第一浮置栅极和耦合电容器的下电容器板的掺杂半导体区域。 掺杂半导体区域包括在有源区的表面处的表面部分和比表面部分的底表面低的侧壁部分。 侧壁部分在有源区域的侧壁上。 电容器绝缘体设置在上电容器板和下电容器板之间。 电容绝缘体包括上部和比上部的底面低的侧壁部。

公开(公告)号：US07858466B2

公开(公告)日：2010-12-28

申请号：US11682621

申请日：2007-03-06

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823857 ,  H01L21/823892

Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.

Abstract translation: 一种制造不同电压装置的方法主要包括在高电压装置区域中形成至少一个高电压阱，在低电压装置区域中形成至少一个N阱，在低电压装置区域中形成至少一个P阱 ，高压器件区域中的源/漏极阱以及p型衬底中的隔离区中的隔离阱。 通过调制离子掺杂分布来调整击穿电压。 此外，调整注入导电离子的参数，以将导电离子注入到高电压器件区域和低电压器件区域中。 在器件之间的隔离区域中形成的隔离阱用于在高电压器件区域上形成的分离器件和在低电压器件区域上形成的器件。 HV栅极氧化物层的厚度比用于调制高电压器件和低电压器件的阈值电压的LV栅极氧化物层的厚度厚。

公开(公告)号：US20130256772A1

公开(公告)日：2013-10-03

申请号：US13437503

申请日：2012-04-02

Applicant: Ching-Hung Fu ,  Chun-Yao Ko ,  Tuo-Hsin Chien ,  Ting-Chen Hsu

Inventor： Ching-Hung Fu ,  Chun-Yao Ko ,  Tuo-Hsin Chien ,  Ting-Chen Hsu

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L21/0223 ,  H01L21/265 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32055 ,  H01L21/76205 ,  H01L21/76213 ,  H01L21/76224 ,  H01L21/76237 ,  H01L27/11517 ,  H01L27/11558 ,  H01L28/40 ,  H01L28/60 ,  H01L29/42324 ,  H01L29/66825

Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.

Abstract translation: 器件包括有源区和耦合电容。 电容器包括作为耦合电容器的上电容器板的第一浮置栅极和耦合电容器的下电容器板的掺杂半导体区域。 掺杂半导体区域包括在有源区的表面处的表面部分和比表面部分的底表面低的侧壁部分。 侧壁部分在有源区域的侧壁上。 电容器绝缘体设置在上电容器板和下电容器板之间。 电容绝缘体包括上部和比上部的底面低的侧壁部。

公开(公告)号：US07615826B2

公开(公告)日：2009-11-10

申请号：US11427773

申请日：2006-06-29

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu G. Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu G. Lin ,  Ta-yung Yang

IPC: H01L23/62

CPC classification number: H01L27/0259

Abstract: An electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided. The semiconductor structure has multi-stage protection semiconductor circuit function and adjustable discharge capacity. The single-trigger or multi-trigger semiconductor structure may be fabricated by using the conventional semiconductor process, and can be applied to IC semiconductor design and to effectively protect the important semiconductor devices and to prevent the semiconductor devices from ESD damage. In particular, the present invention can meet the requirements of high power semiconductor device and has better protection function compared to conventional ESD protection circuit. In the present invention, a plurality of N-wells or P-wells connected in parallel are used to adjust the discharge capacity of various wells in the P-substrate so as to improve the ESD protection capability and meet different power standards.

Abstract translation: 提供具有可调单触发或多触发电压的静电放电（ESD）保护装置。 半导体结构具有多级保护半导体电路功能和可调放电容量。 单触发或多触发半导体结构可以通过使用传统的半导体工艺制造，并且可以应用于IC半导体设计并且有效地保护重要的半导体器件并且防止半导体器件受到ESD损坏。 特别地，本发明可以满足大功率半导体器件的要求，与传统的ESD保护电路相比具有更好的保护功能。 在本发明中，使用并联连接的多个N阱或P阱来调整P基板中的各个阱的放电容量，以提高ESD保护能力并满足不同的功率标准。

公开(公告)号：US20080290410A1

公开(公告)日：2008-11-27

申请号：US11913044

申请日：2005-10-14

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.

Abstract translation: 提供了具有隔离结构的MOSFET。 N型MOSFET包括设置在P型衬底中的第一N型掩埋层和P型外延层。 P型FET包括第二N型掩埋层和设置在P型衬底中的P型外延层。 第一N型掩埋层和P型外延层提供FET之间的隔离。 此外，设置在P型外延层中的多个分离的P型区域进一步提供隔离效果。 在第一厚电场氧化物层和第一P型区域之间存在用于提高N型FET的击穿电压的第一间隙。 在第二厚场氧化物层和第二N阱之间存在第二间隙，用于提高P型FET的击穿电压。

公开(公告)号：US20070117328A1

公开(公告)日：2007-05-24

申请号：US11622429

申请日：2007-01-11

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

IPC: H01L21/336 ,  H01L29/94

CPC classification number: H01L29/7811 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/1095

Abstract: A structure of a vertical transistor with field region is provided. The vertical transistor comprises a field-doping region formed in a substrate next to a core region of the vertical transistor By modulating the doping density, length, and geometrical pattern of the field region, and by connecting the field region to respective well of rim core regions of the vertical transistor, the present invention realizes a stable breakdown voltage with short length of the field region. Therefore, the device area and the manufacturing cost can be reduced.

Abstract translation: 提供具有场区域的垂直晶体管的结构。 垂直晶体管包括通过调制场区域的掺杂密度，长度和几何图案，并且通过将场区域连接到边缘芯的相应阱，形成在靠近垂直晶体管的芯区域的衬底中的场掺杂区域 垂直晶体管的区域，本发明实现了场区域的短长度的稳定的击穿电压。 因此，可以减少设备面积和制造成本。

公开(公告)号：US20070096255A1

公开(公告)日：2007-05-03

申请号：US11567349

申请日：2006-12-06

Applicant: CHIH-FENG HUANG ,  TUO-HSIN CHIEN

Inventor： CHIH-FENG HUANG ,  TUO-HSIN CHIEN

IPC: H01L29/00

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L27/0802

Abstract: A high resistance CMOS resistor with a relatively small die size is provided. The CMOS resistor includes a p-field region disposed in a n-well of a substrate and a pair of p-type contact regions respectively disposed beside a field oxide layer in the n-well. The pair of p-type contact regions are respectively connected to two sides of the p-field region as a first ohmic contact and a second ohmic contact for the CMOS resistor. The CMOS resistor according to the present invention has a resistance of, for example, 10 kΩ-20 kΩ per square.

Abstract translation: 提供了具有相对小的管芯尺寸的高电阻CMOS电阻器。 CMOS电阻器包括设置在衬底的n阱中的p场区域和分别设置在n阱中的场氧化物层旁边的一对p型接触区域。 一对p型接触区域分别连接到p场区域的两侧作为第一欧姆接触和用于CMOS电阻器的第二欧姆接触。 根据本发明的CMOS电阻器具有例如每平方10kOmega-20kOmega的电阻。