- 专利标题: Semiconductor device with a non-erasable memory and/or a nonvolatile memory
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申请号: US11057682申请日: 2005-02-15
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公开(公告)号: US07206216B2公开(公告)日: 2007-04-17
- 发明人: Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
- 申请人: Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: Reed Smith LLP
- 代理商 Stanley P. Fisher, Esq.; Juan Carlos A. Marquez, Esq.
- 优先权: JP2004-043948 20040220; JP2005-001979 20050107
- 主分类号: G11C11/00
- IPC分类号: G11C11/00
摘要:
A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
公开/授权文献
- US20050185445A1 Semiconductor device 公开/授权日:2005-08-25
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