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1.发明申请Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效具有不可擦除存储器和/或非易失性存储器的半导体器件公开(公告)号：US20070159871A1
公开(公告)日：2007-07-12
申请号：US11715918
申请日：2007-03-09
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。
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公开(公告)号：US07206216B2
公开(公告)日：2007-04-17
申请号：US11057682
申请日：2005-02-15
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
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公开(公告)号：US20050185445A1
公开(公告)日：2005-08-25
申请号：US11057682
申请日：2005-02-15
IPC分类号： G11C13/00 , G06F13/00 , G11C11/00 , G11C16/02 , G11C16/10 , G11C16/26 , G11C16/34 , G11C19/08 , H01L27/10 , H01L27/105
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。
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4.发明授权Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效具有不可擦除存储器和/或非易失性存储器的半导体器件公开(公告)号：US07385838B2
公开(公告)日：2008-06-10
申请号：US11715918
申请日：2007-03-09
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。
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公开(公告)号：US08319204B2
公开(公告)日：2012-11-27
申请号：US12373185
申请日：2006-07-21
申请人： Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
发明人： Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
CPC分类号： G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.
摘要翻译： 作为存储单元区域中的存储元件RM，使用由存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫族化物材料制成的记录层52， 使得位于记录层52的下电极TP侧的第一层52a中的Ga或In的浓度高于位于上电极53侧的第二层52b的相应浓度。 例如，记录层形成为使得第二层中的Ga或In的含量比第一层的含量低5原子％以上。 此外，提供了在设定操作和复位操作中可以反转上电极和下电极之间的电压极性的电路。
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公开(公告)号：US20100072451A1
公开(公告)日：2010-03-25
申请号：US12373185
申请日：2006-07-21
申请人： Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
发明人： Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
CPC分类号： G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.
摘要翻译： 作为存储单元区域中的存储元件RM，使用由存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫族化物材料制成的记录层52， 使得位于记录层52的下电极TP侧的第一层52a中的Ga或In的浓度高于位于上电极53侧的第二层52b的相应浓度。 例如，记录层形成为使得第二层中的Ga或In的含量比第一层的含量低5原子％以上。 此外，提供了在设定操作和复位操作中可以反转上电极和下电极之间的电压极性的电路。
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公开(公告)号：US20060198183A1
公开(公告)日：2006-09-07
申请号：US11337648
申请日：2006-01-24
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C13/0004 , G11C29/50016 , G11C2213/79
摘要： With a semiconductor device using a phase change material, in particular, an increase in the number of circuit elements associated with a testing function is checked to the minimum, and an easier test on the semiconductor device is implemented. When a retention test and so forth are conducted on a phase change element, for example, a generated voltage VS1 of a set bit-line voltage power supply, VG_set, provided originally for use in a set operation, is used as a voltage to be applied to the phase change element, and timing when the voltage VS1 is applied to the phase change element is generated by a read/test timing generation circuit TG_rd_test, provided originally to execute a read operation of the phase change element. By so doing, it becomes possible to check an increase in the number of circuit elements, and to conduct the retention test accelerated on a voltage basis with ease.
摘要翻译： 对于使用相变材料的半导体器件，特别地，将与测试功能相关联的电路元件的数量的增加最小化，并且实现对半导体器件的更容易的测试。 当在相变元件上进行保持测试等时，例如，原来用于设定操作的设定位线电压电源VG_set的发电电压VS 1被用作电压 应用于相变元件，并且通过最初为执行相变元件的读取操作而提供的读取/测试定时产生电路TG_rd_test产生电压VS1施加到相变元件的定时。 通过这样做，可以检查电路元件的数量的增加，并且容易地在基于电压的基础上进行加速的保持测试。
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公开(公告)号：US20060274593A1
公开(公告)日：2006-12-07
申请号：US11501118
申请日：2006-08-09
申请人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
发明人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
IPC分类号： G11C17/18
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/009 , G11C2213/76 , G11C2213/79
摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.
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公开(公告)号：US07123535B2
公开(公告)日：2006-10-17
申请号：US11002245
申请日：2004-12-03
申请人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
发明人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
IPC分类号： G11C17/18
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/009 , G11C2213/76 , G11C2213/79
摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.
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公开(公告)号：US07098478B2
公开(公告)日：2006-08-29
申请号：US11168872
申请日：2005-06-29
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
IPC分类号： H01L29/72
CPC分类号： H01L27/11 , H01L27/0688 , H01L27/1104
摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.
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