发明授权
US07214552B2 Eliminating systematic process yield loss via precision wafer placement alignment
有权
通过精密的晶片放置校准消除系统过程产量损失
- 专利标题： Eliminating systematic process yield loss via precision wafer placement alignment
- 专利标题（中）： 通过精密的晶片放置校准消除系统过程产量损失
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申请号： US10992982申请日： 2004-11-19
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公开(公告)号： US07214552B2公开(公告)日： 2007-05-08
- 发明人: Christopher Devany , Charles E. Venditti
- 申请人： Christopher Devany , Charles E. Venditti
- 申请人地址： US VA Sandston
- 专利权人： Infineon Technologies Richmond, LP
- 当前专利权人： Infineon Technologies Richmond, LP
- 当前专利权人地址： US VA Sandston
- 代理机构： Brinks Hofer Gilson & Lione
- 主分类号： G01R31/26
- IPC分类号： G01R31/26
摘要：
A method for a semiconductor process includes correlating yield loss for the performance of a processing step in a semiconductor manufacturing process with the mechanical placement of the semiconductor substrate and, based on the correlation, placing semiconductor substrates in a position with sufficient placement precision to reduce yield loss below a predetermined threshold.
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