Eliminating systematic process yield loss via precision wafer placement alignment
    1.
    发明授权
    Eliminating systematic process yield loss via precision wafer placement alignment 有权
    通过精密的晶片放置校准消除系统过程产量损失

    公开(公告)号:US07214552B2

    公开(公告)日:2007-05-08

    申请号:US10992982

    申请日:2004-11-19

    IPC分类号: G01R31/26

    摘要: A method for a semiconductor process includes correlating yield loss for the performance of a processing step in a semiconductor manufacturing process with the mechanical placement of the semiconductor substrate and, based on the correlation, placing semiconductor substrates in a position with sufficient placement precision to reduce yield loss below a predetermined threshold.

    摘要翻译: 一种半导体工艺的方法包括将半导体制造工艺中的处理步骤的性能与半导体衬底的机械放置相关联的屈服损耗,并且基于相关性,将半导体衬底放置在具有足够的放置精度的位置以降低产量 损失低于预定阈值。