发明授权
- 专利标题: Method of fabricating transistor of DRAM semiconductor device
- 专利标题(中): 制造DRAM半导体器件晶体管的方法
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申请号: US10922055申请日: 2004-08-18
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公开(公告)号: US07223649B2公开(公告)日: 2007-05-29
- 发明人: Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
- 申请人: Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
- 申请人地址: KR Suwon-si, Gyeonggi-do
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si, Gyeonggi-do
- 代理机构: Marger Johnson & McCollom, P.C.
- 优先权: KR10-2003-0057836 20030821
- 主分类号: H01L21/336
- IPC分类号: H01L21/336 ; H01L21/8238 ; H01L21/8242
摘要:
Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
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