Invention Grant
US07231567B2 Method and/or apparatus for performing static timing analysis on a chip in scan mode with multiple scan clocks
有权
用于以具有多个扫描时钟的扫描模式在芯片上执行静态时序分析的方法和/或装置
- Patent Title: Method and/or apparatus for performing static timing analysis on a chip in scan mode with multiple scan clocks
- Patent Title (中): 用于以具有多个扫描时钟的扫描模式在芯片上执行静态时序分析的方法和/或装置
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Application No.: US10789883Application Date: 2004-02-27
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Publication No.: US07231567B2Publication Date: 2007-06-12
- Inventor: Alon Saado , Linley Young
- Applicant: Alon Saado , Linley Young
- Applicant Address: US CA San Diego
- Assignee: Via Telecom Co., Ltd.
- Current Assignee: Via Telecom Co., Ltd.
- Current Assignee Address: US CA San Diego
- Agent Christopher P. Maiorana, PC
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
An apparatus comprising a circuit configured to be tested and a plurality of test blocks within the circuit. Each of the test blocks generally comprises (i) a plurality of sequential elements and (ii) a plurality of logic elements. Each of the test blocks are configured to operate (a) in a first mode comprising a shift mode and (b) a second mode comprising a capture mode. The shift mode generally operates with multiple scan clocks that are clocked simultaneously. The capture mode generally operates with multiple scan clocks, but only one of which is toggled at a time.
Public/Granted literature
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