发明授权
US07233523B2 Optimized layout for multi-bit memory banks each with two data latches and two arithmetic circuits
有权
多位存储库的优化布局，每个存储库都有两个数据锁存器和两个运算电路
- 专利标题： Optimized layout for multi-bit memory banks each with two data latches and two arithmetic circuits
- 专利标题（中）： 多位存储库的优化布局，每个存储库都有两个数据锁存器和两个运算电路
-
申请号： US10503619申请日： 2002-02-28
-
公开(公告)号： US07233523B2公开(公告)日： 2007-06-19
- 发明人: Tsutomu Nakajima , Keiichi Yoshida
- 申请人： Tsutomu Nakajima , Keiichi Yoshida
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Miles & Stockbridge P.C.
- 国际申请： PCT/JP02/01845 WO 20020228
- 国际公布： WO03/073429 WO 20030904
- 主分类号： G11C11/34
- IPC分类号： G11C11/34
摘要：
A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.
公开/授权文献
- US20050157548A1 Nonvolatile semiconductor storage device 公开/授权日：2005-07-21
信息查询
