公开(公告)号：US07515450B2

公开(公告)日：2009-04-07

申请号：US11802168

申请日：2007-05-21

申请人： Tsutomu Nakajima ,  Keiichi Yoshida

发明人： Tsutomu Nakajima ,  Keiichi Yoshida

IPC分类号： G11C5/02

CPC分类号： G11C11/412 ,  G11C11/5642 ,  G11C16/26

摘要： A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.

摘要翻译： 基于用于存储两个或更多位的信息的多级存储技术的闪速存储器1具有四个存储体2a至2d。 例如，在存储体2a的左侧，沿着存储体2a的一个短边设置有数据锁存器6a，而在右侧，沿着存储体2a的另一个短边设置数据锁存器6b。 在数据锁存器6a，6b的下侧设有运算电路7a，7b。 数据锁存器6a，6b分别由SRAM形成。 感测闩锁5a相对于感测闩锁行的中心在左右方向上分为一半。 分频检测锁存器5a经由分别沿着存储体2a的两个短边分配的信号线与数据锁存器6a，6b相连。

公开(公告)号：US20070223275A1

公开(公告)日：2007-09-27

申请号：US11802168

申请日：2007-05-21

申请人： Tsutomu Nakajima ,  Keiichi Yoshida

发明人： Tsutomu Nakajima ,  Keiichi Yoshida

IPC分类号： G11C14/00

CPC分类号： G11C11/412 ,  G11C11/5642 ,  G11C16/26

摘要： A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.

摘要翻译： 基于用于存储两个或更多位的信息的多级存储技术的闪速存储器1具有四个存储体2a至2d。 例如，在存储体2a的左侧，沿着存储体2a的一个短边设置数据锁存器6a，而在右侧，沿着另一个短边设置数据锁存器6b， 银行2 a。 在数据锁存器6a，6b的下侧设有运算电路7a，7b。 数据锁存器6a，6b分别由SRAM形成。 感测锁定器5a相对于感测闩锁行的中心在左右方向上被分成一半。 划分的检测锁存器5a通过分别沿着存储体2a的两个短边分配的信号线与数据锁存器6a，6b连接。

公开(公告)号：US07233523B2

公开(公告)日：2007-06-19

申请号：US10503619

申请日：2002-02-28

申请人： Tsutomu Nakajima ,  Keiichi Yoshida

发明人： Tsutomu Nakajima ,  Keiichi Yoshida

IPC分类号： G11C11/34

CPC分类号： G11C11/412 ,  G11C11/5642 ,  G11C16/26

摘要： A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.

摘要翻译： 基于用于存储两个或更多位的信息的多级存储技术的闪速存储器1具有四个存储体2a至2d。 例如，在存储体2a的左侧，沿着存储体2a的一个短边设置数据锁存器6a，而在右侧，沿着另一个短边设置数据锁存器6b， 银行2 a。 在数据锁存器6a，6b的下侧设有运算电路7a，7b。 数据锁存器6a，6b分别由SRAM形成。 感测锁定器5a相对于感测闩锁行的中心在左右方向上被分成一半。 划分的检测锁存器5a通过分别沿着存储体2a的两个短边分配的信号线与数据锁存器6a，6b连接。

公开(公告)号：US20050157548A1

公开(公告)日：2005-07-21

申请号：US10503619

申请日：2002-02-28

申请人： Tsutomu Nakajima ,  Keiichi Yoshida

发明人： Tsutomu Nakajima ,  Keiichi Yoshida

IPC分类号： G11C11/56 ,  G11C16/26 ,  G11C16/04

CPC分类号： G11C11/412 ,  G11C11/5642 ,  G11C16/26

摘要： A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.

摘要翻译： 基于用于存储两个或更多位的信息的多级存储技术的闪速存储器1具有四个存储体2a至2d。 例如，在存储体2a的左侧，沿着存储体2a的一个短边设置数据锁存器6a，而在右侧，沿着另一个短边设置数据锁存器6b， 银行2 a。 在数据锁存器6a，6b的下侧设有运算电路7a，7b。 数据锁存器6a，6b分别由SRAM形成。 感测锁定器5a相对于感测闩锁行的中心在左右方向上被分成一半。 划分的检测锁存器5a通过分别沿着存储体2a的两个短边分配的信号线与数据锁存器6a，6b连接。

公开(公告)号：US20080246963A1

公开(公告)日：2008-10-09

申请号：US12062871

申请日：2008-04-04

申请人： Tsutomu Nakajima

发明人： Tsutomu Nakajima

IPC分类号： G01N15/02

CPC分类号： G01N15/0205

摘要： A particle counting method is provided whereby a liquid sample is radiated by a laser light, scattered light produced by causing the laser light to hit a particle in the liquid sample is detected by a photoelectric conversion element, and a sample value which is the output of the photoelectric conversion element is sequentially compared to a threshold preset for each particle size range, thereby counting the number of particles for each particle size range, the method comprising: a timer start-up step for starting a timer of a predetermined time when the sample value becomes smaller than a threshold of a minimum particle size for the first time and for sequentially holding the maximum value of the sample value; and a timer extension step for restarting the timer to sequentially hold the maximum value of the sample value when the sample value at the time-out of the timer start-up step is larger than the threshold of the minimum particle size.

摘要翻译： 提供一种粒子计数方法，通过激光照射液体样品，通过光电转换元件检测使得激光撞击液体样品中的颗粒而产生的散射光，并将作为输出的样品值 将光电转换元件顺序地与针对每个粒度范围预设的阈值进行比较，从而对每个粒度范围的粒子数进行计数，该方法包括：定时器启动步骤，用于在样本 值变得小于第一次的最小粒径的阈值，并且顺序地保持样本值的最大值; 以及定时器延长步骤，用于当所述定时器启动步骤超时时的所述采样值大于所述最小粒度的阈值时，重新启动所述定时器以顺序保持所述采样值的最大值。

公开(公告)号：US20080002480A1

公开(公告)日：2008-01-03

申请号：US11896912

申请日：2007-09-06

申请人： Tsutomu Nakajima ,  Satoshi Noda ,  Kenji Kozakai ,  Atsushi Tokairin

发明人： Tsutomu Nakajima ,  Satoshi Noda ,  Kenji Kozakai ,  Atsushi Tokairin

IPC分类号： G11C7/10

CPC分类号： G11C29/84 ,  G11C29/82

摘要： A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.

摘要翻译： 提供不需要每次对任何故障进行抢救的访问地址与故障地址进行比较的非易失性存储装置。 该装置具有存储器阵列，用于向存储器阵列输入数据和从存储器阵列输出数据的数据寄存器以及控制电路。 控制电路在响应于读取数据的指令将多组数据从存储器阵列传送到数据寄存器之后，从传送到数据寄存器的多组数据中取出拯救数据，并执行处理 取代数据寄存器上相应的故障地址的取出救援数据，使数据寄存器上的数据能够提供给外部。 当数据从任何存储器阵列传送到任何数据寄存器上时，读取数据中的任何有故障的数据将被替换为数据寄存器中的数据，每次提供访问地址时，不需要检查读取访问地址是否有故障 从外面。

公开(公告)号：US20070118739A1

公开(公告)日：2007-05-24

申请号：US10580952

申请日：2004-12-22

申请人： Masataka Togashi ,  Tsugihiko Ono ,  Tsutomu Nakajima

发明人： Masataka Togashi ,  Tsugihiko Ono ,  Tsutomu Nakajima

IPC分类号： H04L9/00

CPC分类号： G06Q10/10 ,  H04L9/3263 ,  H04L9/3297 ,  H04L2209/56 ,  H04L2209/60 ,  H04L2209/805

摘要： It is an object to provide a certification system designed for security patrol, for example, that certifies a patrolled time and a patrolled site in security patrol rounds. It is another object to certify the time when an image was taken and the site where the image was taken, for example, by attaching information about certified time and certified site to the image. The certification system includes a GPS satellite 10 that supplies location information on the earth, a weather satellite 20 that supplies weather information on the earth, information processing equipment 30 that is carried in security patrol rounds, a certificate issuing server 40 that certifies time information and location information, an information storage server 50 that stores certified time information and certified location information as well as an image with the certified time information and certified location information attached thereto, a verification unit 60 that verifies the time when the image was taken and the site where the image was taken, and a network 70 that interconnects the information processing equipment 30, the certificate issuing server 40, the information storage server 50, and the verification unit 60.

摘要翻译： 目的是提供一个为安全巡逻而设计的认证系统，例如，在安全巡逻中证明巡逻时间和巡逻地点。 另一个对象是证明拍摄图像的时间和拍摄图像的位置，例如，通过将关于认证时间和认证的站点的信息附加到图像上。 该认证系统包括提供地球上的位置信息的GPS卫星10，在地球上提供天气信息的气象卫星20，安全巡逻中携带的信息处理设备30，证明时间信息的证书发行服务器40以及 位置信息，存储认证时间信息和认证位置信息的信息存储服务器50以及附有经认证的时间信息和认证位置信息的图像，验证图像拍摄时间和验证单元60的图像 拍摄图像的位置以及将信息处理设备30，证书发行服务器40，信息存储服务器50和验证单元60互连的网络70。

公开(公告)号：US5906532A

公开(公告)日：1999-05-25

申请号：US504011

申请日：1995-07-19

申请人： Tsutomu Nakajima ,  Yoshihiro Hayashi

发明人： Tsutomu Nakajima ,  Yoshihiro Hayashi

IPC分类号： B24B37/04 ,  B24B37/30 ,  B24B37/32 ,  H01L21/304 ,  B24B41/06

CPC分类号： B24B37/30

摘要： The method for polishing a semiconductor substrate includes the steps of (a) forming a flowing liquid layer between a semiconductor substrate and a substrate holder to thereby support the semiconductor substrate therebetween by surface tension of the flowing liquid layer, and (b) compressing the semiconductor substrate onto a polishing cloth including process liquid therein. The method ensures that a semiconductor substrate is not damaged at a reverse surface thereof and also that a semiconductor substrate is not contaminated by particles contained in process liquid, because the flowing liquid layer prevents particles of process liquid from entering between the semiconductor substrate and the substrate holder.

摘要翻译： 用于研磨半导体衬底的方法包括以下步骤：（a）在半导体衬底和衬底保持器之间形成流动的液体层，从而通过流动的液体层的表面张力来支撑半导体衬底，以及（b）压缩半导体 衬底到包括其中的处理液的抛光布上。 该方法确保半导体衬底在其反面不被损坏，并且半导体衬底也不被工艺液体中包含的颗粒污染，因为流动的液体层防止工艺液体的颗粒进入半导体衬底和衬底之间 持有人

公开(公告)号：US09325826B2

公开(公告)日：2016-04-26

申请号：US14399237

申请日：2012-06-20

申请人： Hisayuki Mukae ,  Hiroshi Koyama ,  Tsutomu Nakajima

发明人： Hisayuki Mukae ,  Hiroshi Koyama ,  Tsutomu Nakajima

IPC分类号： H04M1/00 ,  H04M1/725 ,  H04W84/06 ,  H04W88/06 ,  H02J7/00 ,  H04B7/185

CPC分类号： H04M1/72527 ,  H02J7/0052 ,  H02J7/0054 ,  H02J2007/0001 ,  H04B7/1851 ,  H04B7/1853 ,  H04W84/06 ,  H04W88/06

摘要： A device that can realize satellite communication with a popularized mobile phone in a case a large number of users communicate at a same time such as in a case where disaster strikes and the like. An external battery for charging a mobile phone includes a satellite antenna for performing satellite communication via a satellite communication channel and a satellite communication unit which causes the mobile phone to perform the satellite communication via the satellite antenna. The mobile phone and the external battery are connected with a cable and the like, and thereby a satellite communication terminal is configured.

摘要翻译： 在大量用户同时进行通信的情况下，例如在灾难等的情况下，能够实现与普及的移动电话的卫星通信的装置。 用于对移动电话充电的外部电池包括用于经由卫星通信信道执行卫星通信的卫星天线和使得移动电话经由卫星天线执行卫星通信的卫星通信单元。 移动电话和外部电池与电缆等连接，从而配置卫星通信终端。

公开(公告)号：US08101683B2

公开(公告)日：2012-01-24

申请号：US12790269

申请日：2010-05-28

申请人： Shinji Irifune ,  Tsutomu Nakajima ,  Kenji Yamamoto

发明人： Shinji Irifune ,  Tsutomu Nakajima ,  Kenji Yamamoto

IPC分类号： C08L83/04 ,  C08J3/03

CPC分类号： C08J3/03 ,  C08G77/12 ,  C08G77/20 ,  C08J2383/04 ,  C08L83/04 ,  C08L83/00

摘要： An addition-curable silicone emulsion that exhibits stable curability even with a small amount of platinum. The curable emulsion composition is composed of an emulsion A and an emulsion B described below which are mixed together at the time of use, wherein the ratio of [number-average particle size of dispersed particles in emulsion A]/[number-average particle size of dispersed particles in emulsion B] is within a range from 0.4 to 2.0. The emulsion A comprises a specific alkenyl group-containing organopolysiloxane, a specific organohydrogenpolysiloxane, a nonionic surfactant, a polyvinyl alcohol and water, wherein the number-average particle size of the dispersed particles is within a range from 300 to 1,000 nm. The emulsion B comprises a specific alkenyl group-containing organopolysiloxane, a platinum-based complex, a nonionic surfactant, a polyvinyl alcohol and water, wherein the number-average particle size of the dispersed particles is within a range from 300 to 1,000 nm.

摘要翻译： 即使使用少量铂也显示稳定的固化性的可加成固化的硅氧烷乳液。 可固化乳液组合物由使用时混合在一起的乳液A和下述乳液B组成，其中[乳液A中分散颗粒的数均粒径] / [数均粒径 的分散颗粒在乳液B中]在0.4至2.0的范围内。 乳液A包含特定的含烯基的有机聚硅氧烷，特定的有机氢聚硅氧烷，非离子表面活性剂，聚乙烯醇和水，其中分散粒子的数均粒径在300〜1000nm的范围内。 乳液B包含特定的含烯基的有机聚硅氧烷，铂系配合物，非离子表面活性剂，聚乙烯醇和水，其中分散粒子的数均粒径在300〜1000nm的范围内。