Invention Grant
- Patent Title: Apparatuses and associated methods for improved solder joint reliability
- Patent Title (中): 改善焊点可靠性的装置和相关方法
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Application No.: US11139223Application Date: 2005-05-27
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Publication No.: US07242084B2Publication Date: 2007-07-10
- Inventor: Chee Wai Wong , Cheng Siew Tay
- Applicant: Chee Wai Wong , Cheng Siew Tay
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Kathy J. Ortiz
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
Apparatuses and associated methods to improve integrated circuit packaging are generally described. More specifically, apparatuses and associated methods to improve solder joint reliability are described. In this regard, according to one example embodiment, one or more strengthening pin(s) are coupled to the periphery of a package substrate, the strengthening pin(s) capable of coupling to a circuit board.
Public/Granted literature
- US20060267217A1 Apparatuses and associated methods for improved solder joint reliability Public/Granted day:2006-11-30
Information query
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