发明授权
US07250359B2 Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
有权
使用梯度GeSi层和平面化控制Si中Ge中的穿透位错密度
- 专利标题: Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
- 专利标题(中): 使用梯度GeSi层和平面化控制Si中Ge中的穿透位错密度
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申请号: US10022689申请日: 2001-12-17
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公开(公告)号: US07250359B2公开(公告)日: 2007-07-31
- 发明人: Eugene A. Fitzgerald
- 申请人: Eugene A. Fitzgerald
- 申请人地址: US MA Cambridge
- 专利权人: Massachusetts Institute of Technology
- 当前专利权人: Massachusetts Institute of Technology
- 当前专利权人地址: US MA Cambridge
- 代理机构: Goodwin Procter LLP
- 主分类号: H01L21/20
- IPC分类号: H01L21/20
摘要:
A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.
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