发明授权
US07256479B2 Method to manufacture a universal footprint for a package with exposed chip
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制造具有裸露芯片的封装的通用尺寸的方法
- 专利标题： Method to manufacture a universal footprint for a package with exposed chip
- 专利标题（中）： 制造具有裸露芯片的封装的通用尺寸的方法
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申请号： US11035918申请日： 2005-01-13
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公开(公告)号： US07256479B2公开(公告)日： 2007-08-14
- 发明人: Jonathan A. Noquil , Connie Tangpuz , Romel Manatad , Stephen Martin , Rajeev Joshi , Venkat Iyer
- 申请人： Jonathan A. Noquil , Connie Tangpuz , Romel Manatad , Stephen Martin , Rajeev Joshi , Venkat Iyer
- 申请人地址： US ME South Portland
- 专利权人： Fairchild Semiconductor Corporation
- 当前专利权人： Fairchild Semiconductor Corporation
- 当前专利权人地址： US ME South Portland
- 代理机构： Townsend and Townsend and Crew LLP
- 主分类号： H01L23/495
- IPC分类号： H01L23/495
摘要：
A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.
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