公开(公告)号：US20060151861A1

公开(公告)日：2006-07-13

申请号：US11035918

申请日：2005-01-13

申请人： Jonathan Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

发明人： Jonathan Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

IPC分类号： H01L23/495

CPC分类号： H01L23/36 ,  H01L23/488 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K3/341 ,  H05K2201/09681 ,  H05K2201/10166 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.

摘要翻译： 公开了一种半导体管芯封装。 它可以包括具有第一表面和第二表面的半导体管芯和引线框架结构。 模制材料可以围绕模具的至少一部分和引线框架结构的至少一部分形成。 可焊层可以在模制材料的外表面和半导体管芯的第一表面上。

公开(公告)号：US20050280126A1

公开(公告)日：2005-12-22

申请号：US11213182

申请日：2005-08-25

申请人： Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

发明人： Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

IPC分类号： H01L23/48 ,  H01L21/76 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52

CPC分类号： H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

公开(公告)号：US20050224940A1

公开(公告)日：2005-10-13

申请号：US11145081

申请日：2005-06-03

申请人： Consuelo Tangpuz ,  Romel Manatad ,  Margie Rios ,  Erwin Cruz

发明人： Consuelo Tangpuz ,  Romel Manatad ,  Margie Rios ,  Erwin Cruz

IPC分类号： H01L21/60 ,  H01L23/31 ,  H01L23/485 ,  H01L23/495 ,  H01L23/544 ,  H01L23/02

CPC分类号： H01L23/49582 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49586 ,  H01L23/544 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18301 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/81205 ,  H01L2224/05599

摘要： A packaging assembly for semiconductor devices and a method for making such packaging is described. The invention provides a non-Pb bump design during a new flip-chip method of packaging. The design uses special conductive materials in a stud form, rather than a solder ball containing Pb. This configuration maintains a desirable solder thickness between the die and the leadframe and forms a high standoff by restricting solder wettabilty on the leadframe side. This configuration also absorbs any stress and protects the die from cracking. The invention also provides methods for making such semiconductor packages.

公开(公告)号：US20070161151A1

公开(公告)日：2007-07-12

申请号：US11364399

申请日：2006-02-28

申请人： Ruben Madrid ,  Romel Manatad

发明人： Ruben Madrid ,  Romel Manatad

IPC分类号： H01L21/00

CPC分类号： H01L23/49562 ,  H01L23/4334 ,  H01L24/17 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/17051 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.

摘要翻译： 发明要求保护的是具有双暴露表面的封装半导体器件和制造器件的方法。 热夹子和一个或多个源垫通过用于封装器件的非导电模制材料暴露在器件的相对两端。 热夹子和源垫可以是顶部或底部暴露的。 栅极，源极和漏极引线通过模制材料暴露，并且所有引线与底部暴露表面共面。 该器件可以具有多个半导体管芯或各种尺寸的管芯，同时仍然具有单一的，恒定的占地面积。 制造方法需要将半导体管芯附接到热夹子，然后将具有附接的热夹子的管芯附接到引线框架。 然后将所得到的器件依次模制，标记，修剪和分割，从而形成具有双暴露表面的封装半导体器件。

公开(公告)号：US20050167848A1

公开(公告)日：2005-08-04

申请号：US10702792

申请日：2003-11-05

申请人： Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

发明人： Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

IPC分类号： H01L23/48 ,  H01L21/76 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52

CPC分类号： H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

摘要翻译： 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。

公开(公告)号：US20080036056A1

公开(公告)日：2008-02-14

申请号：US11693141

申请日：2007-03-29

申请人： Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

发明人： Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

摘要翻译： 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。

公开(公告)号：US07256479B2

公开(公告)日：2007-08-14

申请号：US11035918

申请日：2005-01-13

申请人： Jonathan A. Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

发明人： Jonathan A. Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

IPC分类号： H01L23/495

CPC分类号： H01L23/36 ,  H01L23/488 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K3/341 ,  H05K2201/09681 ,  H05K2201/10166 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.

摘要翻译： 公开了一种半导体管芯封装。 它可以包括具有第一表面和第二表面的半导体管芯和引线框架结构。 模制材料可以围绕模具的至少一部分和引线框架结构的至少一部分形成。 可焊层可以在模制材料的外表面和半导体管芯的第一表面上。

公开(公告)号：US08624393B2

公开(公告)日：2014-01-07

申请号：US13404317

申请日：2012-02-24

申请人： Suku Kim ,  James Murphy ,  Matthew Reynolds ,  Romel Manatad ,  Jan Mancelita ,  Michael Gruenhagen

发明人： Suku Kim ,  James Murphy ,  Matthew Reynolds ,  Romel Manatad ,  Jan Mancelita ,  Michael Gruenhagen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/74 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.

摘要翻译： 描述了半导体器件中使用的晶片的局部变薄方法和由这些方法形成的结构。 该方法使半导体晶片的背面薄的局部区域形成具有在晶片（或管芯）内重复的双向通道设计的凹槽，使得没有直通道线穿过晶片（或管芯）。 双向图案设计保持通道不与晶片的晶体取向对齐。 然后通过将适当尺寸的焊球落入凹槽中然后通过焊球落下工艺填充凹陷，然后退火晶片以回流焊球并使其平坦化。 回流工艺开始从底部向上填充凹槽，从而避免了空隙形成和回流焊料中形成的空气阱。 还描述了其它实施例。

公开(公告)号：US20070241431A1

公开(公告)日：2007-10-18

申请号：US11689971

申请日：2007-03-22

申请人： Romel Manatad

发明人： Romel Manatad

IPC分类号： H01L23/495

CPC分类号： H01L23/49861 ,  H01L23/49844 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/40225 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01058 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/37099

摘要： A semiconductor package is disclosed. The package includes a leadframe structure comprising a die attach region and plurality of leads. A molding material is molded around at least a portion of the leadframe structure, and comprises a window. A semiconductor die comprising an edge is mounted on the die attach region and is within the window. A gap is present between the edge of the semiconductor die and the molding material.

摘要翻译： 公开了半导体封装。 封装包括引线框架结构，其包括管芯附接区域和多个引线。 围绕引线框架结构的至少一部分模制成型材料，并且包括窗口。 包括边缘的半导体管芯安装在管芯附接区域上并且在窗口内。 在半导体管芯的边缘和模制材料之间存在间隙。

公开(公告)号：US20060231933A1

公开(公告)日：2006-10-19

申请号：US11446342

申请日：2006-06-01

申请人： Elsie Cabahug ,  Marvin Gestole ,  Margie Tumulak-Rios ,  Lilith Montayre ,  Romel Manatad

发明人： Elsie Cabahug ,  Marvin Gestole ,  Margie Tumulak-Rios ,  Lilith Montayre ,  Romel Manatad

IPC分类号： H01L23/495

CPC分类号： H01L23/49562 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.