Invention Grant
US07257693B2 Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system
失效
多处理器计算系统采用压缩缓存行的信息和能够在所述系统中使用的处理器
- Patent Title: Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system
- Patent Title (中): 多处理器计算系统采用压缩缓存行的信息和能够在所述系统中使用的处理器
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Application No.: US10759922Application Date: 2004-01-15
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Publication No.: US07257693B2Publication Date: 2007-08-14
- Inventor: Chris J. Newburn , Ram Huggahalli , Herbert H J Hum , Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum
- Applicant: Chris J. Newburn , Ram Huggahalli , Herbert H J Hum , Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F12/06
- IPC: G06F12/06
Abstract:
Cache coherency rules for a multi-processor computing system that is capable of working with compressed cache lines' worth of information are described. A multi-processor computing system that is capable of working with compressed cache lines' worth of information is also described. The multi-processor computing system includes a plurality of hubs for communicating with various computing system components and for compressing/decompressing cache lines' worth of information. A processor that is capable of labeling cache lines' worth of information in accordance with the cache coherency rules is described. A processor that includes a hub as described above is also described.
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