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1.发明授权Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system 失效多处理器计算系统采用压缩缓存行的信息和能够在所述系统中使用的处理器公开(公告)号：US07257693B2
公开(公告)日：2007-08-14
申请号：US10759922
申请日：2004-01-15
Applicant: Chris J. Newburn , Ram Huggahalli , Herbert H J Hum , Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum
Inventor： Chris J. Newburn , Ram Huggahalli , Herbert H J Hum , Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum
IPC: G06F12/06
CPC classification number: G06F12/0886 , G06F12/0802 , G06F12/0864 , G06F2212/401
Abstract: Cache coherency rules for a multi-processor computing system that is capable of working with compressed cache lines' worth of information are described. A multi-processor computing system that is capable of working with compressed cache lines' worth of information is also described. The multi-processor computing system includes a plurality of hubs for communicating with various computing system components and for compressing/decompressing cache lines' worth of information. A processor that is capable of labeling cache lines' worth of information in accordance with the cache coherency rules is described. A processor that includes a hub as described above is also described.
Abstract translation: 描述了能够处理压缩高速缓存行的信息量的多处理器计算系统的缓存一致性规则。 还描述了能够处理压缩高速缓存行的信息的多处理器计算系统。 多处理器计算系统包括用于与各种计算系统组件进行通信并用于压缩/解压缩高速缓存行的信息价值的多个集线器。 描述了能够根据高速缓存一致性规则来标记高速缓存线值的信息的处理器。 还描述了包括如上所述的集线器的处理器。
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2.发明授权Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information 有权处理器和内存控制器能够在采用压缩缓存行的信息量的计算系统中使用公开(公告)号：US07512750B2
公开(公告)日：2009-03-31
申请号：US10750715
申请日：2003-12-31
Applicant: Chris J. Newburn , Ram Huggahalli , Herbert H J Hum , Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum
Inventor： Chris J. Newburn , Ram Huggahalli , Herbert H J Hum , Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum
IPC: G06F12/00
CPC classification number: G06F12/0802 , G06F12/0886 , G06F2212/401
Abstract: A memory controller is described that comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information. A processor and a memory controller integrated on a same semiconductor die is also described. The memory controller comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information.
Abstract translation: 描述了包括压缩映射高速缓存的存储器控制器。 压缩映射缓存用于存储标识缓存行的信息值的信息，该信息已被另一个高速缓存行的信息压缩。 还描述了集成在同一半导体管芯上的处理器和存储器控制器。 存储器控制器包括压缩映射高速缓存。 压缩映射缓存用于存储标识缓存行的信息值的信息，该信息已被另一个高速缓存行的信息压缩。
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Patent Agency Ranking
公开(公告)号：US07162584B2
公开(公告)日：2007-01-09
申请号：US10747474
申请日：2003-12-29
Applicant: Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum
Inventor： Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum
IPC: G06F12/00
CPC classification number: G06F12/0862 , G06F12/121 , G06F2212/401 , G06F2212/6028 , Y02D10/13
Abstract: According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU), a cache memory coupled to the CPU and a cache controller coupled to the cache memory. The cache memory includes a plurality of compressible cache lines to store additional data. The cache controller includes compression logic to compress one or more of the plurality of cache lines into compressed cache lines, and hint logic to store hint information in unused space within the compressed cache lines.
Abstract translation: 根据一个实施例，公开了一种计算机系统。 计算机系统包括中央处理单元（CPU），耦合到CPU的高速缓存存储器和耦合到高速缓冲存储器的高速缓存控制器。 高速缓冲存储器包括多个可压缩的高速缓存线以存储附加数据。 高速缓存控制器包括将多个高速缓存线中的一个或多个压缩成压缩高速缓存线的压缩逻辑，以及提示逻辑，用于将提示信息存储在压缩高速缓存行内的未使用空间中。
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4.发明授权公开(公告)号：US08316360B2
公开(公告)日：2012-11-20
申请号：US11537585
申请日：2006-09-29
Applicant: Byoungro So , Anwar M. Ghuloum , Youfeng Wu
Inventor： Byoungro So , Anwar M. Ghuloum , Youfeng Wu
IPC: G06F9/45
CPC classification number: G06F8/451
Abstract: Methods and apparatus to optimize the parallel execution of software processes are disclosed. An example method includes receiving a first software process that processes a set of data, locating a first primitive in the first software process, and decomposing the first primitive into a first set of one or more sub-primitives. The example methods and apparatus additionally perform static fusion and dynamic fusion to optimize software processes for execution in parallel processing systems.
Abstract translation: 公开了优化并行执行软件过程的方法和装置。 示例性方法包括接收处理一组数据的第一软件过程，在第一软件过程中定位第一原语，以及将第一原语分解成一个或多个子原语的第一集合。 示例性方法和设备另外执行静态融合和动态融合以优化用于并行处理系统中的执行的软件过程。
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5.发明申请公开(公告)号：US20080127145A1
公开(公告)日：2008-05-29
申请号：US11537585
申请日：2006-09-29
Applicant: Byoungro So , Anwar M. Ghuloum , Youfeng Wu
Inventor： Byoungro So , Anwar M. Ghuloum , Youfeng Wu
IPC: G06F9/45
CPC classification number: G06F8/451
Abstract: Methods and apparatus to optimize the parallel execution of software processes are disclosed. An example method includes receiving a first software process that processes a set of data, locating a first primitive in the first software process, and decomposing the first primitive into a first set of one or more sub-primitives. The example methods and apparatus additionally perform static fusion and dynamic fusion to optimize software processes for execution in parallel processing systems.
Abstract translation: 公开了优化并行执行软件过程的方法和装置。 示例性方法包括接收处理一组数据的第一软件过程，在第一软件过程中定位第一原语，以及将第一原语分解成一个或多个子原语的第一集合。 示例性方法和设备另外执行静态融合和动态融合以优化用于并行处理系统中的执行的软件过程。
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公开(公告)号：US07162583B2
公开(公告)日：2007-01-09
申请号：US10747470
申请日：2003-12-29
Applicant: Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum , Guei-Yuan Lueh , Victor Ying
Inventor： Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum , Guei-Yuan Lueh , Victor Ying
IPC: G06F12/00
CPC classification number: G06F12/0802 , G06F12/0862 , G06F2212/401 , H03M7/30
Abstract: According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU), a cache memory coupled to the CPU and a cache controller, coupled to the cache memory. The cache memory includes a plurality of compressible cache lines to store additional data. The cache controller reorders a cache line after each access to the cache line prior to the compression of the cache line into a compressed cache line.
Abstract translation: 根据一个实施例，公开了一种计算机系统。 计算机系统包括中央处理单元（CPU），耦合到CPU的高速缓冲存储器和耦合到高速缓冲存储器的高速缓存控制器。 高速缓冲存储器包括多个可压缩的高速缓存线以存储附加数据。 在将高速缓存行压缩到压缩高速缓存行之前，高速缓存控制器在对高速缓存行进行每次访问之后重新排序高速缓存行。
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公开(公告)号：US07143238B2
公开(公告)日：2006-11-28
申请号：US10676480
申请日：2003-09-30
Applicant: Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum , Ram Huggahalli , Chris J. Newburn
Inventor： Ali-Reza Adl-Tabatabai , Anwar M. Ghuloum , Ram Huggahalli , Chris J. Newburn
IPC: G06F12/00
CPC classification number: G06F12/0886 , G06F2212/401
Abstract: A computer system includes a central processing unit (CPU) and a cache memory coupled to the CPU. The cache memory includes a plurality of compressible cache lines to store additional data.
Abstract translation: 计算机系统包括中央处理单元（CPU）和耦合到CPU的高速缓冲存储器。 高速缓冲存储器包括多个可压缩的高速缓存线以存储附加数据。
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