Invention Grant
- Patent Title: Method of manufacturing a transistor
- Patent Title (中): 制造晶体管的方法
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Application No.: US10898484Application Date: 2004-07-22
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Publication No.: US07265011B2Publication Date: 2007-09-04
- Inventor: Jae-Man Yoon , Dong-gun Park , Makoto Yoshida , Gyo-Young Jin , Jeong-dong Choe , Sang-Yeon Han
- Applicant: Jae-Man Yoon , Dong-gun Park , Makoto Yoshida , Gyo-Young Jin , Jeong-dong Choe , Sang-Yeon Han
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Marger Johnson & McCollom, P.C.
- Priority: KR10-2003-0060331 20030829
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.
Public/Granted literature
- US20050048729A1 Method of manufacturing a transistor Public/Granted day:2005-03-03
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