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    Method of manufacturing a transistor
    1.
    发明申请
    Method of manufacturing a transistor 失效
    制造晶体管的方法

    公开(公告)号：US20050048729A1

    公开(公告)日：2005-03-03

    申请号：US10898484

    申请日：2004-07-22

    申请人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

    发明人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

    IPC分类号： H01L21/334 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/66537

    摘要： A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

    摘要翻译： 根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区， 并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。 该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成 栅极区域中的第三杂质区域。 该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。

    Method of manufacturing a transistor
    2.
    发明授权
    Method of manufacturing a transistor 失效
    制造晶体管的方法

    公开(公告)号：US07265011B2

    公开(公告)日：2007-09-04

    申请号：US10898484

    申请日：2004-07-22

    申请人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

    发明人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/66537

    摘要： A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

    摘要翻译： 根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区， 并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。 该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成 栅极区域中的第三杂质区域。 该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。

    Method of forming fin field effect transistor
    3.
    发明授权
    Method of forming fin field effect transistor 有权
    形成鳍式场效应晶体管的方法

    公开(公告)号：US07056781B2

    公开(公告)日：2006-06-06

    申请号：US11014212

    申请日：2004-12-15

    申请人： Jae-Man Yoon ,  Gyo-Young Jin ,  Hee-Soo Kang ,  Dong-Gun Park

    发明人： Jae-Man Yoon ,  Gyo-Young Jin ,  Hee-Soo Kang ,  Dong-Gun Park

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78609

    摘要： According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.

    摘要翻译： 根据一些实施例，在半导体衬底上的侧壁的曝光状态下形成鳍型有源区。 在有源区的上部和侧壁上形成栅极绝缘层，并且器件隔离膜将活性区域包围到有源区的上部高度。 侧壁由形成在器件隔离膜上的开口部分部分露出。 开口部分填充有部分覆盖有源区的上部的导电层，形成栅电极。 源极和漏极区域在栅电极不是的有源区域的一部分上。 可以容易地分离栅极电极，并且可以显着地减少由蚀刻副产物引起的问题，并且可以防止沟道区域的漏电流和电场集中在边缘部分上。

    Double gate field effect transistor and method of manufacturing the same
    5.
    发明申请
    Double gate field effect transistor and method of manufacturing the same 失效
    双栅场效应晶体管及其制造方法

    公开(公告)号：US20060134868A1

    公开(公告)日：2006-06-22

    申请号：US11316307

    申请日：2005-12-21

    申请人： Jae-Man Yoon ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

    发明人： Jae-Man Yoon ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

    摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

    摘要翻译： 提供双栅场效应晶体管及其制造方法。 制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜 掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。 因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。

    Method of forming fin field effect transistor
    6.
    发明申请
    Method of forming fin field effect transistor 有权
    形成鳍式场效应晶体管的方法

    公开(公告)号：US20050153490A1

    公开(公告)日：2005-07-14

    申请号：US11014212

    申请日：2004-12-15

    申请人： Jae-Man Yoon ,  Gyo-Young Jin ,  Hee-Soo Kang ,  Dong-Gun Park

    发明人： Jae-Man Yoon ,  Gyo-Young Jin ,  Hee-Soo Kang ,  Dong-Gun Park

    IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/00

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78609

    摘要： According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.

    摘要翻译： 根据一些实施例，在半导体衬底上的侧壁的曝光状态下形成鳍型有源区。 在有源区的上部和侧壁上形成栅极绝缘层，并且器件隔离膜将活性区域包围到有源区的上部高度。 侧壁由形成在器件隔离膜上的开口部分部分露出。 开口部分填充有部分覆盖有源区的上部的导电层，形成栅电极。 源极和漏极区域在栅电极不是的有源区域的一部分上。 可以容易地分离栅极电极，并且可以显着地减少由蚀刻副产物引起的问题，并且可以防止沟道区域的漏电流和电场集中在边缘部分上。