公开(公告)号：US07265011B2

公开(公告)日：2007-09-04

申请号：US10898484

申请日：2004-07-22

申请人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

发明人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/66537

摘要： A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

摘要翻译： 根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区， 并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。 该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成 栅极区域中的第三杂质区域。 该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。

公开(公告)号：US20050048729A1

公开(公告)日：2005-03-03

申请号：US10898484

申请日：2004-07-22

申请人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

发明人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

IPC分类号： H01L21/334 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/66537

摘要： A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

摘要翻译： 根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区， 并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。 该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成 栅极区域中的第三杂质区域。 该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。

公开(公告)号：US07332386B2

公开(公告)日：2008-02-19

申请号：US11084922

申请日：2005-03-21

申请人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

发明人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/785 ,  H01L21/26513 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/78624

摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.

摘要翻译： 翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。 翅片在基底上并沿着和垂直方向横向延伸。 栅电极覆盖翅片的一侧和顶部。 栅绝缘层位于栅电极和鳍之间。 翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。 翅片的源极区域具有与鳍片的漏极区域不同的宽度。

公开(公告)号：US20050269629A1

公开(公告)日：2005-12-08

申请号：US11084922

申请日：2005-03-21

申请人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

发明人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L21/26513 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/78624

摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.

摘要翻译： 翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。 翅片在基底上并沿着和垂直方向横向延伸。 栅电极覆盖翅片的一侧和顶部。 栅绝缘层位于栅电极和鳍之间。 翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。 翅片的源极区域具有与鳍片的漏极区域不同的宽度。

公开(公告)号：US07015106B2

公开(公告)日：2006-03-21

申请号：US10917026

申请日：2004-08-11

申请人： Jae-Man Yoon ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

发明人： Jae-Man Yoon ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

IPC分类号： H01L21/336 ,  H01L21/00 ,  H01L21/338

CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

公开(公告)号：US20060134868A1

公开(公告)日：2006-06-22

申请号：US11316307

申请日：2005-12-21

申请人： Jae-Man Yoon ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

发明人： Jae-Man Yoon ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

摘要翻译： 提供双栅场效应晶体管及其制造方法。 制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜 掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。 因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。

公开(公告)号：US07154154B2

公开(公告)日：2006-12-26

申请号：US10683782

申请日：2003-10-10

申请人： Shin-Ae Lee ,  Dong-gun Park ,  Chang-sub Lee ,  Jeong-dong Choe ,  Sung-min Kim ,  Seong-ho Kim

发明人： Shin-Ae Lee ,  Dong-gun Park ,  Chang-sub Lee ,  Jeong-dong Choe ,  Sung-min Kim ,  Seong-ho Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553

摘要： MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.

摘要翻译： MOS晶体管具有限定在半导体衬底的一部分中的有源区，有源区上的栅电极和衬底中的漏极和源极区。 第一和第二横向突起从栅电极的相应侧壁的下部延伸。 漏极区域在第一横向突起下方具有第一轻掺杂漏极区域，与第一轻掺杂漏极区域相邻的第二轻掺杂漏极区域和与第二轻掺杂漏极区域相邻的重掺杂漏极区域。 源极区域类似地在第二横向突起下方具有第一轻掺杂源极区域，与第一轻掺杂源极区域相邻的第二轻掺杂源极区域和与第二轻掺杂源极区域相邻的重掺杂源极区域 。 第二轻掺杂区域比第一轻掺杂区域深，并且栅电极可以具有倒置T形。

公开(公告)号：US20070096217A1

公开(公告)日：2007-05-03

申请号：US11560556

申请日：2006-11-16

申请人： Shin-Ae Lee ,  Dong-gun Park ,  Chang-sub Lee ,  Jeong-dong Choe ,  Sung-min Kim ,  Seong-ho Kim

发明人： Shin-Ae Lee ,  Dong-gun Park ,  Chang-sub Lee ,  Jeong-dong Choe ,  Sung-min Kim ,  Seong-ho Kim

IPC分类号： H01L29/94

CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553

摘要： MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.

摘要翻译： MOS晶体管具有限定在半导体衬底的一部分中的有源区，有源区上的栅电极和衬底中的漏极和源极区。 第一和第二横向突起从栅电极的相应侧壁的下部延伸。 漏极区域在第一横向突起下方具有第一轻掺杂漏极区域，与第一轻掺杂漏极区域相邻的第二轻掺杂漏极区域和与第二轻掺杂漏极区域相邻的重掺杂漏极区域。 源极区域类似地在第二横向突起下方具有第一轻掺杂源极区域，与第一轻掺杂源极区域相邻的第二轻掺杂源极区域和与第二轻掺杂源极区域相邻的重掺杂源极区域 。 第二轻掺杂区域比第一轻掺杂区域深，并且栅电极可以具有倒置T形。

公开(公告)号：US07015549B2

公开(公告)日：2006-03-21

申请号：US10706755

申请日：2003-11-12

申请人： Sung-min Kim ,  Dong-gun Park ,  Chang-sub Lee ,  Jeong-dong Choe ,  Shin-ae Lee ,  Seong-ho Kim

发明人： Sung-min Kim ,  Dong-gun Park ,  Chang-sub Lee ,  Jeong-dong Choe ,  Shin-ae Lee ,  Seong-ho Kim

IPC分类号： H01L29/772

CPC分类号： H01L21/76264 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78639 ,  H01L29/78654

摘要： An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active region. An epitaxial silicon layer extends from the active region through the insulation layer to a substrate beneath the insulation layer.

摘要翻译： 集成电路结构可以包括隔离结构，其将集成电路基板的有源区域与相邻的有源区域隔离，以及从隔离结构延伸到有源区域下方的绝缘层。 外延硅层从有源区延伸穿过绝缘层到绝缘层下方的衬底。

公开(公告)号：US07288823B2

公开(公告)日：2007-10-30

申请号：US11316307

申请日：2005-12-21

申请人： Jae-Mun Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

发明人： Jae-Mun Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor includes forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

摘要翻译： 提供双栅场效应晶体管及其制造方法。 制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜 掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。 因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。