Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Invention Grant

US07268024B2 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors 有权

Title translation: 包含应变通道部分耗尽，完全耗尽和多栅极晶体管的绝缘体上半导体芯片

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Patent Title: Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
Patent Title (中): 包含应变通道部分耗尽，完全耗尽和多栅极晶体管的绝缘体上半导体芯片
Application No.: US10999564

Application Date: 2004-11-29
Publication No.: US07268024B2

Publication Date: 2007-09-11
Inventor: Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
Applicant: Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
Applicant Address: TW Hsin-Chu
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
Current Assignee Address: TW Hsin-Chu
Agency: Slater & Matsil, L.L.P.
Main IPC: H01L21/84
IPC: H01L21/84

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Abstract:

In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Abstract(Chinese):

根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。

Public/Granted literature

US20050093067A1 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors Public/Granted day:2005-05-05

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/84	.....衬底不是半导体的，例如绝缘体