公开(公告)号：US07268024B2

公开(公告)日：2007-09-11

申请号：US10999564

申请日：2004-11-29

Applicant: Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L21/84

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7854

Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Abstract translation: 根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。 在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。 包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。 例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。

公开(公告)号：US20050093067A1

公开(公告)日：2005-05-05

申请号：US10999564

申请日：2004-11-29

Applicant: Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7854

Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

公开(公告)号：US06867433B2

公开(公告)日：2005-03-15

申请号：US10426566

申请日：2003-04-30

Applicant: Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7854

Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Abstract translation: 根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。 在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。 包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。 例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。