发明授权
US07271626B1 Suppression of parasitic ringing at the output of a switched capacitor DC/DC converter
有权
在开关电容器DC / DC转换器的输出端抑制寄生振荡
- 专利标题: Suppression of parasitic ringing at the output of a switched capacitor DC/DC converter
- 专利标题(中): 在开关电容器DC / DC转换器的输出端抑制寄生振荡
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申请号: US10974177申请日: 2004-10-27
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公开(公告)号: US07271626B1公开(公告)日: 2007-09-18
- 发明人: Alexander Burinskiy , Nathanael Griesert , Arun Rao , William J. McIntyre , John Philip Parry
- 申请人: Alexander Burinskiy , Nathanael Griesert , Arun Rao , William J. McIntyre , John Philip Parry
- 申请人地址: US CA Santa Clara
- 专利权人: National Semiconductor Corporation
- 当前专利权人: National Semiconductor Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Darby & Darby P.C.
- 代理商 Davin Chin
- 主分类号: H03K3/00
- IPC分类号: H03K3/00
摘要:
A multi-stage transistor circuit is provided in which the multiple transistor stages are coupled in parallel and switched individually in sequence by a series arrangement of buffers. Each buffer drives the gate of a corresponding stage of the multi-stage transistor circuit with a gating signal that is delayed by each buffer. Optionally, the voltage of the gating signal can be varied. Each transistor stage may comprise one or more transistors in parallel. A switched capacitor DC/DC converter incorporating the multi-stage transistor circuit is provided in which parasitic ringing at the output is substantially reduced or eliminated. Additionally, the multi-stage transistor circuit is well suited for implementing an adaptive non-overlapping gating signal generator for complementarily driving a series arrangement of multi-stage transistors. An adaptive gating signal generator incorporating the multi-stage transistor circuit provides the minimum dead time between the gating signals that will ensure under all conditions that the multi-stage transistors will not be on at the same time.
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