发明授权
US07286382B1 Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability
有权
具有增强的全故障覆盖存储器单元可测性的存储器中的分段数据线方案
- 专利标题： Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability
- 专利标题（中）： 具有增强的全故障覆盖存储器单元可测性的存储器中的分段数据线方案
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申请号： US11590333申请日： 2006-10-31
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公开(公告)号： US07286382B1公开(公告)日： 2007-10-23
- 发明人: Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
- 申请人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
- 申请人地址： US CA San Jose
- 专利权人： Xilinx, Inc.
- 当前专利权人： Xilinx, Inc.
- 当前专利权人地址： US CA San Jose
- 代理商 William L. Paradice, III; Thomas A. Ward
- 主分类号： G11C15/00
- IPC分类号： G11C15/00 ; G11C11/00
摘要：
A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.
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