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    Method and system for configuring an integrated circuit
    1.
    发明授权
    Method and system for configuring an integrated circuit 有权
    用于配置集成电路的方法和系统

    公开(公告)号：US07314174B1

    公开(公告)日：2008-01-01

    申请号：US10970964

    申请日：2004-10-22

    申请人： Vasisht Mantra Vadi ,  David P. Schultz ,  Steven P. Young ,  Jennifer Wong

    发明人： Vasisht Mantra Vadi ,  David P. Schultz ,  Steven P. Young ,  Jennifer Wong

    IPC分类号： G06K7/10 ,  G06K9/36 ,  G06K9/80

    CPC分类号： H03K19/177

    摘要： A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.

    摘要翻译： 一种用于在集成电路中编程配置存储单元的系统。 该系统包括：一组数据寄存器，其中该组的成员具有固定数量的配置位的临时存储; 和多行，每行具有多个列，其中使用固定数量的配置位对所选列和所选行中的配置存储单元进行编程。

    Reconfiguration port for dynamic reconfiguration-system monitor interface
    6.
    发明授权
    Reconfiguration port for dynamic reconfiguration-system monitor interface 有权
    动态重新配置系统监控接口的重新配置端口

    公开(公告)号：US07233532B2

    公开(公告)日：2007-06-19

    申请号：US10836961

    申请日：2004-04-30

    申请人： Vasisht Mantra Vadi ,  David P. Schultz ,  John D. Logue ,  John McGrath ,  Anthony Collins ,  F. Erich Goetting

    发明人： Vasisht Mantra Vadi ,  David P. Schultz ,  John D. Logue ,  John McGrath ,  Anthony Collins ,  F. Erich Goetting

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： H03K19/17776 ,  H03K19/17744 ,  H03K19/17752 ,  H03K19/1776 ,  H03K19/17764

    摘要： Method and apparatus for an interface to a system monitor (1600) is described. A controller (102) accessible via a port interface thereof (110) is configured for read/write access to configuration memory cells (1500) and for read access to status registers (1602). The configuration memory cells (1500) are addressable via a first address space, and the status registers (1602) are addressable via a second address space different from the first address space. The port interface (110) is configured to receive a plurality of signals including a data address signal (124) and a data clock signal (121). The data address signal (124) has address information for accessing either the first address space or the second address space.

    摘要翻译： 描述了用于系统监视器（1600）的接口的方法和装置。 经由其端口接口（110）可访问的控制器（102）被配置用于对配置存储器单元（1500）进行读/写访问以及对状态寄存器（1602）的读取访问。 配置存储器单元（1500）可通过第一地址空间寻址，并且状态寄存器（1602）可通过与第一地址空间不同的第二地址空间来寻址。 端口接口（110）被配置为接收包括数据地址信号（124）和数据时钟信号（121）的多个信号。 数据地址信号（124）具有访问第一地址空间或第二地址空间的地址信息。

    Method and apparatus for a multiplexed address line driver
    7.
    发明授权
    Method and apparatus for a multiplexed address line driver 有权
    多路复用地址线驱动器的方法和装置

    公开(公告)号：US07196940B1

    公开(公告)日：2007-03-27

    申请号：US10971394

    申请日：2004-10-22

    申请人： Vasisht Mantra Vadi ,  David P. Schultz

    发明人： Vasisht Mantra Vadi ,  David P. Schultz

    IPC分类号： G11C7/10

    CPC分类号： G11C7/20 ,  G11C8/08

    摘要： A method and apparatus for multiplexing various voltage magnitudes onto the address line of a memory cell. An address line voltage generator applies complex analog voltage magnitudes to a memory cell address line during Power On Reset (POR) to insure proper memory cell initialization during power up. Once initialized, read and write address select signals are level shifted to be equal to or greater than the read and write voltage magnitudes applied to the memory cell address line to ensure proper operation.

    摘要翻译： 一种用于将各种电压幅度复用到存储器单元的地址线上的方法和装置。 在上电复位（POR）期间，地址线电压发生器将复杂的模拟电压幅值应用于存储单元地址线，以确保上电期间适当的存储单元初始化。 一旦初始化，读取和写入地址选择信号被电平移动到等于或大于施加到存储单元地址线的读取和写入电压幅度，以确保正确的操作。

    Reconfiguration port for dynamic reconfiguration
    8.
    发明授权
    Reconfiguration port for dynamic reconfiguration 有权
    重新配置端口用于动态重新配置

    公开(公告)号：US07218137B2

    公开(公告)日：2007-05-15

    申请号：US10837331

    申请日：2004-04-30

    申请人： Vasisht Mantra Vadi ,  David P. Schultz ,  John D. Logue ,  John McGrath ,  Anthony Collins ,  F. Erich Goetting

    发明人： Vasisht Mantra Vadi ,  David P. Schultz ,  John D. Logue ,  John McGrath ,  Anthony Collins ,  F. Erich Goetting

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17752 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/1776

    摘要： Method and apparatus for dynamic configuration of function block logic of an integrated circuit is described. The integrated circuit includes a reconfiguration port coupled to a controller. The controller is coupled to an array of memory cell. A portion of the array of memory cells is coupled for read/write communication with the controller, and another portion of the array of memory cells is not coupled for read/write communication with the controller. The portion of the array of memory cells is configurable at an operational frequency of the integrated circuit for dynamic reconfiguration of the function block logic of the integrated circuit.

    摘要翻译： 描述了用于集成电路的功能块逻辑的动态配置的方法和装置。 集成电路包括耦合到控制器的重配置端口。 控制器耦合到存储器单元的阵列。 存储器单元阵列的一部分被耦合用于与控制器的读/写通信，并且存储器单元阵列的另一部分不耦合用于与控制器的读/写通信。 存储器单元阵列的部分可以在集成电路的工作频率下配置，用于集成电路的功能块逻辑的动态重新配置。

    Reconfiguration port for dynamic reconfiguration—sub-frame access for reconfiguration
    9.
    发明授权
    Reconfiguration port for dynamic reconfiguration—sub-frame access for reconfiguration 有权
    用于重新配置的动态重新配置 - 子帧访问的重新配置端口

    公开(公告)号：US07126372B2

    公开(公告)日：2006-10-24

    申请号：US10836841

    申请日：2004-04-30

    申请人： Vasisht Mantra Vadi ,  David P. Schultz ,  John D. Logue ,  John McGrath ,  Anthony Collins ,  F. Erich Goetting

    发明人： Vasisht Mantra Vadi ,  David P. Schultz ,  John D. Logue ,  John McGrath ,  Anthony Collins ,  F. Erich Goetting

    IPC分类号： H03K19/173

    CPC分类号： H03K19/173

    摘要： Method and apparatus for sub-frame bit access for reconfiguring a logic block of a programmable logic device is described. A reconfiguration port in communication with a controller is provided. The controller is in communication with configuration memory for configuring the logic block. Configuration information is provided via the reconfiguration port. A single data word stored in the configuration memory is read via the controller, modified with the configuration information, and written back into configuration memory. Accordingly, by reading a single data word, in contrast to an entire frame, on-the-fly reconfiguration is facilitated.

    摘要翻译： 描述了用于重配置可编程逻辑器件的逻辑块的子帧位访问的方法和装置。 提供了与控制器通信的重新配置端口。 控制器与用于配置逻辑块的配置存储器通信。 配置信息通过重配置端口提供。 通过控制器读取存储在配置存储器中的单个数据字，用配置信息进行修改，并写回到配置存储器中。 因此，通过读取单个数据字，与整个帧相反，便于实时重新配置。

    Reconfiguration port for dynamic reconfiguration-controller
    10.
    发明授权
    Reconfiguration port for dynamic reconfiguration-controller 有权
    动态重新配置控制器的重新配置端口

    公开(公告)号：US07109750B2

    公开(公告)日：2006-09-19

    申请号：US10836960

    申请日：2004-04-30

    申请人： Vasisht Mantra Vadi ,  David P. Schultz ,  John D. Logue ,  John McGrath ,  Anthony Collins ,  F. Erich Goetting

    发明人： Vasisht Mantra Vadi ,  David P. Schultz ,  John D. Logue ,  John McGrath ,  Anthony Collins ,  F. Erich Goetting

    IPC分类号： H03K19/173

    CPC分类号： H03K19/173

    摘要： Method and apparatus for a controller for dynamic configuration is described. The controller comprises a port interface, a read/write interface, and a plurality of flip-flops. The flip-flops, couple the port interface to the read/write interface. The port interface is configured to receive a plurality of signals, where portion of the plurality of signals are pipelined through the plurality of flip-flops responsive to a data clock signal of the plurality of signals. This facilitates reading and writing to storage elements at a rate which is at least approximately a frequency of the data clock signal while operating a device at approximately such frequency in which the controller is instantiated.

    摘要翻译： 描述了用于动态配置的控制器的方法和装置。 控制器包括端口接口，读/写接口和多个触发器。 触发器将端口接口耦合到读/写接口。 端口接口被配置为接收多个信号，其中响应于多个信号的数据时钟信号，多个信号的部分通过多个触发器流水线化。 这便于以大约这样的控制器被实例化的频率操作设备的速率，以至少近似于数据时钟信号的频率的速率读取和写入存储元件。