发明授权
- 专利标题: Nanotube-on-gate FET structures and applications
- 专利标题(中): 纳米管栅极FET结构和应用
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申请号: US10811373申请日: 2004-03-26
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公开(公告)号: US07294877B2公开(公告)日: 2007-11-13
- 发明人: Thomas Rueckes , Brent M. Segal , Bernard Vogeli , Darren K. Brock , Venkatachalam C. Jaiprakash , Claude L. Bertin
- 申请人: Thomas Rueckes , Brent M. Segal , Bernard Vogeli , Darren K. Brock , Venkatachalam C. Jaiprakash , Claude L. Bertin
- 申请人地址: US MA Woburn
- 专利权人: Nantero, Inc.
- 当前专利权人: Nantero, Inc.
- 当前专利权人地址: US MA Woburn
- 代理机构: Wilmer Cutler Pickering Hale and Dorr LLP
- 主分类号: H01L51/30
- IPC分类号: H01L51/30
摘要:
Nanotube on gate FET structures and applications of such, including n2 crossbars requiring only 2n control lines. A non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and a channel region of a second semiconductor type of material disposed between the source and drain region. A gate structure is made of at least one of semiconductive or conductive material and is disposed over an insulator over the channel region. A control gate is made of at least one of semiconductive or conductive material. An electromechanically-deflectable nanotube switching element is in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure. The network is such that the nanotube switching element is deflectable into contact with the other of the gate structure and the control gate structure in response to signals being applied to the control gate and one of the source region and drain region. Certain embodiments of the device have an area of about 4 F2. Other embodiments include a release line is positioned in spaced relation to the nanotube switching element, and having a horizontal orientation that is parallel to the orientation of the source and drain diffusions. Other embodiments provide an n2 crossbar array having n2 non-volatile transistor devices, but require only 2n control lines.
公开/授权文献
- US20050056877A1 Nanotube-on-gate fet structures and applications 公开/授权日:2005-03-17
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