- 专利标题: Method of manufacturing semiconductor device having impurity region under isolation region
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申请号: US11493529申请日: 2006-07-27
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公开(公告)号: US07297585B2公开(公告)日: 2007-11-20
- 发明人: Shigenobu Maeda , Toshiaki Iwamatsu , Takashi Ipposhi
- 申请人: Shigenobu Maeda , Toshiaki Iwamatsu , Takashi Ipposhi
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: McDermott Will & Emery LLP
- 优先权: JPP2001-001418 20010109
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238
摘要:
In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
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