发明授权
US07317203B2 Method and monitor structure for detecting and locating IC wiring defects
有权
IC接线缺陷检测和定位的方法和监控结构
- 专利标题： Method and monitor structure for detecting and locating IC wiring defects
- 专利标题（中）： IC接线缺陷检测和定位的方法和监控结构
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申请号： US11189180申请日： 2005-07-25
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公开(公告)号： US07317203B2公开(公告)日： 2008-01-08
- 发明人: Wen-Yi Chen , Jun-Yean Chiu , Chung Lee , Hung-Hon Lui
- 申请人： Wen-Yi Chen , Jun-Yean Chiu , Chung Lee , Hung-Hon Lui
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Tung & Associates
- 主分类号： H01L23/58
- IPC分类号： H01L23/58 ; H01L21/66
摘要：
A 3-dimensional PCM structure and method for using the same for carrying out 3-dimensional integrated circuit wiring electrical testing and failure analysis in an integrated circuit manufacturing process, the method including forming a first metallization layer; carrying out a first wafer acceptance testing (WAT) process to test the electrical continuity of the first metallization layer; forming first metal vias on the first metallization layer conductive portions and a second metallization layer comprising metal islands on the first metal vias wherein the metal islands electrically communicate with the first metallization layer to form a process control monitor (PCM) structure; and, carrying out a second WAT process to test the electrical continuity of the first metallization layer.
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