Invention Grant
- Patent Title: Wafer level chip scale packaging structure and method of fabricating the same
- Patent Title (中): 晶圆级芯片级封装结构及其制造方法
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Application No.: US11152149Application Date: 2005-06-15
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Publication No.: US07319050B2Publication Date: 2008-01-15
- Inventor: Shu-Ming Chang , Lee-Cheng Shen
- Applicant: Shu-Ming Chang , Lee-Cheng Shen
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: TW92131918A 20031114
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will peel or the sacrificial layer material will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.
Public/Granted literature
- US20050230846A1 Wafer level chip scale packaging structure and method of fabricating the same Public/Granted day:2005-10-20
Information query
IPC分类: