公开(公告)号：US08039935B2

公开(公告)日：2011-10-18

申请号：US11652088

申请日：2007-01-11

申请人： Shu-Ming Chang ,  Lee-Cheng Shen ,  Wei-Chung Lo

发明人： Shu-Ming Chang ,  Lee-Cheng Shen ,  Wei-Chung Lo

IPC分类号： H01L23/02

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

摘要翻译： 提供晶片级芯片级封装结构及其制造方法，以使用正常的半导体工艺在凸块下方形成牺牲层。 该凸块用于连接Si晶圆和PCB之间的信号。 牺牲层和相邻层之间的界面是整个结构中最薄弱的部分。 当施加到凸块的应力过载时，牺牲层和相邻层之间的界面将崩溃以消除由Si晶片和PCB的不同热膨胀系数产生的应力。 牺牲层将有助于避免碰撞发生的碰撞以保护Si晶片和PCB之间的电导通。

公开(公告)号：US07319050B2

公开(公告)日：2008-01-15

申请号：US11152149

申请日：2005-06-15

申请人： Shu-Ming Chang ,  Lee-Cheng Shen

发明人： Shu-Ming Chang ,  Lee-Cheng Shen

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will peel or the sacrificial layer material will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

摘要翻译： 公开了晶片级芯片级封装结构及其制造方法，以使用正常的半导体工艺在凸块下方形成牺牲层。 该凸块用于连接Si晶圆和PCB之间的信号。 牺牲层和PCB之间的界面是整个结构中最薄弱的部分。 当施加到凸块的应力过载时，牺牲层和相邻层之间的界面将剥离，或者牺牲层材料将崩溃以消除由Si晶片和PCB的不同热膨胀系数产生的应力。 牺牲层将有助于避免碰撞发生的碰撞以保护Si晶片和PCB之间的电导通。

公开(公告)号：US20050230846A1

公开(公告)日：2005-10-20

申请号：US11152149

申请日：2005-06-15

申请人： Shu-Ming Chang ,  Lee-Cheng Shen

发明人： Shu-Ming Chang ,  Lee-Cheng Shen

IPC分类号： H01L21/60 ,  H01L23/02 ,  H01L23/31 ,  H01L23/48 ,  H01L23/485

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the PCB will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

摘要翻译： 公开了晶片级芯片级封装结构及其制造方法，以使用正常的半导体工艺在凸块下方形成牺牲层。 该凸块用于连接Si晶圆和PCB之间的信号。 牺牲层和PCB之间的界面是整个结构中最薄弱的部分。 当施加到凸块的应力过载时，牺牲层和PCB之间的界面将崩溃，以消除由Si晶片和PCB的不同热膨胀系数产生的应力。 牺牲层将有助于避免碰撞发生的碰撞以保护Si晶片和PCB之间的电导通。

公开(公告)号：US20100289706A1

公开(公告)日：2010-11-18

申请号：US12714637

申请日：2010-03-01

申请人： Tsung-Ying Hsieh ,  Lee-Cheng Shen ,  Chin-Lien Hsu

发明人： Tsung-Ying Hsieh ,  Lee-Cheng Shen ,  Chin-Lien Hsu

IPC分类号： H01Q1/24

CPC分类号： H01Q1/38 ,  H01Q1/2266 ,  H01Q9/0407

摘要： A portable electronic apparatus is provided which includes a first housing, a second housing, a control unit, a display unit, and a wireless communication device. The two housings are rotatably coupled to each other. The control unit is accommodated in the first housing. The display unit is accommodated in the second housing and is connected to the control unit. The wireless communication device is accommodated in the second housing and has a wireless communication module and an antenna. The wireless communication module is connected to the control unit and the antenna, and is configured to perform wireless communication through the antenna under control of the control unit.

摘要翻译： 提供一种便携式电子设备，其包括第一壳体，第二壳体，控制单元，显示单元和无线通信设备。 两个壳体彼此可旋转地联接。 控制单元容纳在第一壳体中。 显示单元容纳在第二壳体中并连接到控制单元。 无线通信装置容纳在第二壳体中并具有无线通信模块和天线。 无线通信模块连接到控制单元和天线，并且被配置为在控制单元的控制下通过天线执行无线通信。

公开(公告)号：US07436683B2

公开(公告)日：2008-10-14

申请号：US11639557

申请日：2006-12-15

申请人： Lee-Cheng Shen

发明人： Lee-Cheng Shen

IPC分类号： H05K1/11

CPC分类号： H01L23/3114 ,  H01L23/5227 ,  H01L24/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

摘要： A wafer level packaging structure with inductors and manufacture method thereof. The method comprises providing a substrate, having several inductors, forming conductive lines and holes to connect the inductors and the wafer, and bonding the substrate and the wafer via bonding pads. Therefore, there are air gaps between the inductors and the wafer, thereby reducing the inductor's dispassion loss and increasing the inductor's quality factor. In addition, the inductors having a high quality factor can be integrated in the wafer containing active/passive components.

摘要翻译： 具有电感器的晶片级封装结构及其制造方法。 该方法包括提供具有多个电感器的衬底，形成导线和孔以连接电感器和晶片，以及通过接合焊盘接合衬底和晶片。 因此，电感器和晶片之间存在气隙，从而降低电感器的消散损耗并增加电感器的品质因数。 此外，具有高品质因数的电感器可以集成在包含有源/无源部件的晶片中。

公开(公告)号：US06998718B2

公开(公告)日：2006-02-14

申请号：US10765961

申请日：2004-01-29

申请人： Shu-Ming Chang ,  Lee-Cheng Shen

发明人： Shu-Ming Chang ,  Lee-Cheng Shen

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the PCB will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

摘要翻译： 公开了晶片级芯片级封装结构及其制造方法，以使用正常的半导体工艺在凸块下方形成牺牲层。 该凸块用于连接Si晶圆和PCB之间的信号。 牺牲层和PCB之间的界面是整个结构中最薄弱的部分。 当施加到凸块的应力过载时，牺牲层和PCB之间的界面将崩溃，以消除由Si晶片和PCB的不同热膨胀系数产生的应力。 牺牲层将有助于避免碰撞发生的碰撞以保护Si晶片和PCB之间的电导通。

公开(公告)号：US20130201650A1

公开(公告)日：2013-08-08

申请号：US13449691

申请日：2012-04-18

申请人： Lee-Cheng SHEN ,  Tsung-Ying HSIEH

发明人： Lee-Cheng SHEN ,  Tsung-Ying HSIEH

IPC分类号： H05K9/00

CPC分类号： H05K9/0024

摘要： A molded radio-frequency (RF) structure with electromagnetic shielding includes a substrate layer, an RF layer, a molded layer and a metal layer. The RF element is disposed on the substrate layer. The molded layer is located on the substrate layer and overlays the RF element. The metal layer is coated on the molded layer, and has an opening located above the RF element.

摘要翻译： 具有电磁屏蔽的模制射频（RF）结构包括基底层，RF层，模制层和金属层。 RF元件设置在基板层上。 模制层位于衬底层上并覆盖RF元件。 金属层涂覆在模制层上，并且具有位于RF元件上方的开口。

公开(公告)号：US08228083B2

公开(公告)日：2012-07-24

申请号：US12609145

申请日：2009-10-30

申请人： Lee-Cheng Shen

发明人： Lee-Cheng Shen

IPC分类号： G01R31/02 ,  G01R31/36

CPC分类号： G01R1/0466 ,  G01R1/18

摘要： The invention discloses a testing system and a testing method, suitable for testing a DUT with double-sided signal pins. The testing system includes a testing platform and a pick-and-place device. The testing platform includes an electromagnetic shielding chamber and a test-bench module. The electromagnetic shielding chamber has an opening. The test-bench module is disposed in-between the electromagnetic shielding chamber. The pick-and-place device is movably disposed above the testing platform. The pick-and-place device includes an electromagnetic shielding cap and a signal transmission structure. When the pick-and-place device places the DUT on the test-bench module, the electromagnetic shielding cap cooperates with the electromagnetic shielding chamber of the testing platform to form an isolated space for isolating the DUT, and furthermore, the signal pin disposed on an upper surface of the DUT can be electrically connected to the test-bench module through the signal transmission structure.

摘要翻译： 本发明公开了一种测试系统和测试方法，适用于使用双面信号引脚测试DUT。 测试系统包括测试平台和拾取和放置设备。 测试平台包括电磁屏蔽室和测试台模块。 电磁屏蔽室具有开口。 测试台模块设置在电磁屏蔽室之间。 拾取和放置装置可移动地设置在测试平台之上。 拾取和放置装置包括电磁屏蔽帽和信号传输结构。 当拾取设备将DUT放置在测试台模块上时，电磁屏蔽帽与测试平台的电磁屏蔽室配合，形成隔离DUT的隔离空间，此外，信号针位于 DUT的上表面可以通过信号传输结构电连接到测试台模块。

公开(公告)号：US20070108629A1

公开(公告)日：2007-05-17

申请号：US11652088

申请日：2007-01-11

申请人： Shu-Ming Chang ,  Lee-Cheng Shen ,  Wei-Chung Lo

发明人： Shu-Ming Chang ,  Lee-Cheng Shen ,  Wei-Chung Lo

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

摘要翻译： 提供晶片级芯片级封装结构及其制造方法，以使用正常的半导体工艺在凸块下方形成牺牲层。 该凸块用于连接Si晶圆和PCB之间的信号。 牺牲层和相邻层之间的界面是整个结构中最薄弱的部分。 当施加到凸块的应力过载时，牺牲层和相邻层之间的界面将崩溃以消除由Si晶片和PCB的不同热膨胀系数产生的应力。 牺牲层将有助于避免碰撞发生的碰撞以保护Si晶片和PCB之间的电导通。

公开(公告)号：US20100283476A1

公开(公告)日：2010-11-11

申请号：US12609145

申请日：2009-10-30

申请人： Lee-Cheng Shen

发明人： Lee-Cheng Shen

IPC分类号： G01R31/02

CPC分类号： G01R1/0466 ,  G01R1/18

摘要： The invention discloses a testing system and a testing method, suitable for testing a DUT with double-sided signal pins. The testing system includes a testing platform and a pick-and-place device. The testing platform includes an electromagnetic shielding chamber and a test-bench module. The electromagnetic shielding chamber has an opening. The test-bench module is disposed in-between the electromagnetic shielding chamber. The pick-and-place device is movably disposed above the testing platform. The pick-and-place device includes an electromagnetic shielding cap and a signal transmission structure. When the pick-and-place device places the DUT on the test-bench module, the electromagnetic shielding cap cooperates with the electromagnetic shielding chamber of the testing platform to form an isolated space for isolating the DUT, and furthermore, the signal pin disposed on an upper surface of the DUT can be electrically connected to the test-bench module through the signal transmission structure.

摘要翻译： 本发明公开了一种测试系统和测试方法，适用于使用双面信号引脚测试DUT。 测试系统包括测试平台和拾取和放置设备。 测试平台包括电磁屏蔽室和测试台模块。 电磁屏蔽室具有开口。 测试台模块设置在电磁屏蔽室之间。 拾取和放置装置可移动地设置在测试平台之上。 拾取和放置装置包括电磁屏蔽帽和信号传输结构。 当拾取设备将DUT放置在测试台模块上时，电磁屏蔽帽与测试平台的电磁屏蔽室配合，形成隔离DUT的隔离空间，此外，信号针位于 DUT的上表面可以通过信号传输结构电连接到测试台模块。