发明授权
- 专利标题： Caching support for direct memory access address translation
- 专利标题（中）： 缓存支持直接内存访问地址转换
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申请号： US10956206申请日： 2004-09-30
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公开(公告)号： US07334107B2公开(公告)日： 2008-02-19
- 发明人: Ioannis Schoinas , Rajesh Madukkarumukumana , Gilbert Neiger , Richard Uhlig , Balaji Vembu
- 申请人： Ioannis Schoinas , Rajesh Madukkarumukumana , Gilbert Neiger , Richard Uhlig , Balaji Vembu
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理商 Philip A. Pedigo
- 主分类号： G06F12/00
- IPC分类号： G06F12/00 ; G06F13/28
摘要：
An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physical address corresponds to a guest domain identified by a guest domain identifier in an input/output (I/O) transaction requested by an I/O device. A register stores an invalidating domain identifier identifying an invalidating domain and an indicator indicating invalidating an entry in the cached entries having a tag.
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