Invention Grant
- Patent Title: Device with stepped source/drain region profile
- Patent Title (中): 具有阶梯式源极/漏极区域剖面的器件
-
Application No.: US11031843Application Date: 2005-01-06
-
Publication No.: US07335959B2Publication Date: 2008-02-26
- Inventor: Giuseppe Curello , Bernhard Sell , Sunit Tyagi , Chris Auth
- Applicant: Giuseppe Curello , Bernhard Sell , Sunit Tyagi , Chris Auth
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94

Abstract:
Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.
Public/Granted literature
- US20060145273A1 Device with stepped source/drain region profile Public/Granted day:2006-07-06
Information query
IPC分类: