- 专利标题: EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same
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申请号: US10997835申请日: 2004-11-24
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公开(公告)号: US07352026B2公开(公告)日: 2008-04-01
- 发明人: Weon-ho Park , Byoung-ho Kim , Hyun-khe Yoo , Seung-beom Yoon , Sung-chul Park , Ju-ri Kim , Kwang-tae Kim , Jeong-wook Han
- 申请人: Weon-ho Park , Byoung-ho Kim , Hyun-khe Yoo , Seung-beom Yoon , Sung-chul Park , Ju-ri Kim , Kwang-tae Kim , Jeong-wook Han
- 申请人地址: KR
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR
- 代理机构: Mills & Onello LLP
- 优先权: KR10-2003-0085766 20031128
- 主分类号: H01L29/788
- IPC分类号: H01L29/788 ; H01L29/76
摘要:
Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.
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