Invention Grant
US07356742B2 Method and apparatus for testing a memory device in quasi-operating conditions
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用于在准操作条件下测试存储器件的方法和装置
- Patent Title: Method and apparatus for testing a memory device in quasi-operating conditions
- Patent Title (中): 用于在准操作条件下测试存储器件的方法和装置
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Application No.: US11107896Application Date: 2005-04-18
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Publication No.: US07356742B2Publication Date: 2008-04-08
- Inventor: Hideyuki Aoki , Takeshi Wada , Masaaki Namba , Noboru Uchida , Shigeki Katsumi , Yuji Wada , Masaaki Mochiduki
- Applicant: Hideyuki Aoki , Takeshi Wada , Masaaki Namba , Noboru Uchida , Shigeki Katsumi , Yuji Wada , Masaaki Mochiduki
- Applicant Address: JP Tokyo JP Tokyo
- Assignee: Renesas Technology Corp.,Hitachi High-Technologies Corporation
- Current Assignee: Renesas Technology Corp.,Hitachi High-Technologies Corporation
- Current Assignee Address: JP Tokyo JP Tokyo
- Agency: Mattingly, Stanger, Malur & Brundidge, P.C.
- Priority: JP11-358305 19991217
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer (PC). The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out form the measurement PC unit; a plurality of performance boards (PFBs) mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chipset LSI (large scale integrated circuit) on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.
Public/Granted literature
- US20050193274A1 Method and apparatus for testing a memory device in quasi-operating conditions Public/Granted day:2005-09-01
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