公开(公告)号：US20050193274A1

公开(公告)日：2005-09-01

申请号：US11107896

申请日：2005-04-18

申请人： Hideyuki Aoki ,  Takeshi Wada ,  Masaaki Namba ,  Noboru Uchida ,  Shigeki Katsumi ,  Yuji Wada ,  Masaaki Mochiduki

发明人： Hideyuki Aoki ,  Takeshi Wada ,  Masaaki Namba ,  Noboru Uchida ,  Shigeki Katsumi ,  Yuji Wada ,  Masaaki Mochiduki

IPC分类号： G01R31/28 ,  G06F12/16 ,  G11C29/56 ,  G06F11/00

CPC分类号： G11C29/56

摘要： A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer. The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out from the measurement PC unit; a plurality of PFBs mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chip set LSI on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.

摘要翻译： 记忆测试系统可以通过使用个人计算机在准操作条件下以低成本准确地屏蔽测试对象。 该系统利用包括测量PC单元的PC测试器，该单元携带用作参考的存储器模块; 信号分配单元，用于分配从测量PC单元取出的信号; 通过使用由信号分配单元分配的信号同时观察安装有相应对象产品的多个PFB; 用于显示正在进行的测试的当前状态的显示面板; 用于产生系统的工作电压的电源; 以及用于控制测试参数和各种分析操作的选择的控制PC。 PC测试器适于将测量PC单元中的PC母板上的芯片组LSI的信号从存储器模块或存储器模块本身的各个存储器中取出，并在准工作条件下进行测试。

公开(公告)号：US07356742B2

公开(公告)日：2008-04-08

申请号：US11107896

申请日：2005-04-18

申请人： Hideyuki Aoki ,  Takeshi Wada ,  Masaaki Namba ,  Noboru Uchida ,  Shigeki Katsumi ,  Yuji Wada ,  Masaaki Mochiduki

发明人： Hideyuki Aoki ,  Takeshi Wada ,  Masaaki Namba ,  Noboru Uchida ,  Shigeki Katsumi ,  Yuji Wada ,  Masaaki Mochiduki

IPC分类号： G11C29/00

CPC分类号： G11C29/56

摘要： A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer (PC). The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out form the measurement PC unit; a plurality of performance boards (PFBs) mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chipset LSI (large scale integrated circuit) on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.

摘要翻译： 记忆测试系统可以通过使用个人计算机（PC）在准操作条件下以低成本准确地屏蔽测试对象。 该系统利用包括测量PC单元的PC测试器，该单元携带用作参考的存储器模块; 信号分配单元，用于分配从测量PC单元取出的信号; 通过使用由信号分配单元分配的信号同时观察安装有相应对象产品的多个性能板（PFB）; 用于显示正在进行的测试的当前状态的显示面板; 用于产生系统的工作电压的电源; 以及用于控制测试参数和各种分析操作的选择的控制PC。 PC测试器适用于将测量PC单元中的PC母板上的芯片组LSI（大规模集成电路）的信号从存储器模块或存储器模块本身的各个存储器中取出， 运行条件。

公开(公告)号：US6138257A

公开(公告)日：2000-10-24

申请号：US115793

申请日：1998-07-15

申请人： Yuji Wada ,  Kaoru Fukuda ,  Yoshio Kamiko ,  Masaaki Mochiduki

发明人： Yuji Wada ,  Kaoru Fukuda ,  Yoshio Kamiko ,  Masaaki Mochiduki

IPC分类号： G01R31/3193 ,  G11C29/56 ,  G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31935 ,  G11C29/56

摘要： Main tester unit tests an IC device for presence of a defect for each of a plurality of addresses of the IC device under predetermined test conditions and stores test results for the individual addresses into a first memory. Curing analysis processing section cures each of the addresses of the IC device determined as defective, on the basis of the test results for the individual addresses stored in the first memory. To this end, the curing analysis processing section may rearrange an address logic of the IC device to replace a physical space of the defective addresses with an extra or redundant address space and thereby place each of the defective addresses in a usable condition. In parallel with the operations by the curing analysis processing section, a defect analysis section acquires, from the main tester unit, the test results for the individual addresses along with data indicative of the predetermined test conditions for storage into a second memory, and analyzes a specific cause of the defect in the IC device on the basis of the stored data in the second memory. With this arrangement, it is possible to acquire information necessary for analyzing the defect in the IC during a curability determining analysis test on a mass production line and thereby can effectively analyze the specific cause of the detected defect.

摘要翻译： 主测试器单元在预定测试条件下测试IC器件以存在IC器件的多个地址中的每一个的缺陷，并将各个地址的测试结果存储到第一存储器中。 基于存储在第一存储器中的各个地址的测试结果，固化分析处理部分固化被确定为有缺陷的IC设备的每个地址。 为此，固化分析处理部分可以重新排列IC设备的地址逻辑，以用额外的或冗余的地址空间替换缺陷地址的物理空间，从而将每个缺陷地址置于可用状态。 与固化分析处理部分的操作并行，缺陷分析部分从主测试器单元获取各个地址的测试结果以及指示用于存储到第二存储器中的预定测试条件的数据，并且分析 基于第二存储器中存储的数据，IC装置中的缺陷的特定原因。 通过这种布置，可以在大规模生产线上的固化性确定分析测试中获取分析IC中的缺陷所需的信息，从而可以有效地分析检测到的缺陷的具体原因。