发明授权
- 专利标题: Low resistance semiconductor process and structures
- 专利标题(中): 低电阻半导体工艺和结构
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申请号: US11305598申请日: 2005-12-16
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公开(公告)号: US07358568B2公开(公告)日: 2008-04-15
- 发明人: Michael J. Hermes , Kunal R. Parekh
- 申请人: Michael J. Hermes , Kunal R. Parekh
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 主分类号: H01L29/76
- IPC分类号: H01L29/76
摘要:
A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along each gate, a plurality of conductive plugs each contacting the wafer, and a BPSG layer overlying the transistor gates and contacting the active area. A portion of the BPSG layer is etched thereby exposing the TEOS caps. A portion of the BPSG layer remains on the active area after completion of the etch. Subsequently, a portion of the TEOS caps are removed to expose the transistor gates and a titanium silicide layer is formed simultaneously to contact the transistor gates and the plugs. An inventive structure resulting from the inventive process is also described.
公开/授权文献
- US20060097327A1 Low resistance semiconductor process and structures 公开/授权日:2006-05-11
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