公开(公告)号：US07259093B2

公开(公告)日：2007-08-21

申请号：US11211853

申请日：2005-08-24

申请人： Michael J. Hermes

发明人： Michael J. Hermes

IPC分类号： H01L21/4763

CPC分类号： H01L21/76804

摘要： A dielectric is formed over a node location on a semiconductor substrate. The dielectric comprises an insulative material over the node location, an insulative polish stop layer over the insulative material, and an insulator layer over the insulative polish stop layer. A contact opening is formed into the insulator layer, the insulative polish stop layer and the insulative material to proximate the node location. A conductive material is deposited over the insulator layer and to within the contact opening. The conductive material and the insulator layer are polished to at least a portion of the insulative polish stop layer. In one implementation and prior to depositing the conductive material, at least a portion of the contact opening is widened with an etching chemistry that is selective to widen it within the insulative material to a degree greater than any widening of the contact opening within the insulative polish stop layer.

摘要翻译： 在半导体衬底上的节点位置上形成电介质。 电介质包括在节点位置上的绝缘材料，绝缘材料上方的绝缘抛光停止层以及绝缘抛光停止层上的绝缘体层。 接触开口形成为绝缘体层，绝缘抛光停止层和绝缘材料以接近节点位置。 导电材料沉积在绝缘体层上并且在接触开口内。 导电材料和绝缘体层被抛光到绝缘抛光止挡层的至少一部分上。 在一个实施方案中，并且在沉积导电材料之前，接触开口的至少一部分用蚀刻化学品加宽，该蚀刻化学品可选择性地将其在绝缘材料内扩大到比绝缘抛光剂内的接触开口的任何加宽度 停止层。

公开(公告)号：US06979641B2

公开(公告)日：2005-12-27

申请号：US10804702

申请日：2004-03-19

申请人： Michael J. Hermes

发明人： Michael J. Hermes

IPC分类号： B24B1/00 ,  B24B7/19 ,  B24B7/30 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76804

摘要： A dielectric is formed over a node location on a semiconductor substrate. The dielectric comprises an insulative material over the node location, an insulative polish stop layer over the insulative material, and an insulator layer over the insulative polish stop layer. A contact opening is formed into the insulator layer, the insulative polish stop layer and the insulative material to proximate the node location. A conductive material is deposited over the insulator layer and to within the contact opening. The conductive material and the insulator layer are polished to at least a portion of the insulative polish stop layer. In one implementation and prior to depositing the conductive material, at least a portion of the contact opening is widened with an etching chemistry that is selective to widen it within the insulative material to a degree greater than any widening of the contact opening within the insulative polish stop layer.

公开(公告)号：US07358568B2

公开(公告)日：2008-04-15

申请号：US11305598

申请日：2005-12-16

申请人： Michael J. Hermes ,  Kunal R. Parekh

发明人： Michael J. Hermes ,  Kunal R. Parekh

IPC分类号： H01L29/76

CPC分类号： H01L21/76897 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823475

摘要： A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along each gate, a plurality of conductive plugs each contacting the wafer, and a BPSG layer overlying the transistor gates and contacting the active area. A portion of the BPSG layer is etched thereby exposing the TEOS caps. A portion of the BPSG layer remains on the active area after completion of the etch. Subsequently, a portion of the TEOS caps are removed to expose the transistor gates and a titanium silicide layer is formed simultaneously to contact the transistor gates and the plugs. An inventive structure resulting from the inventive process is also described.

摘要翻译： 一种用于形成半导体器件的方法包括以下步骤：提供半导体衬底组件，其包括其中形成有有效区的半导体晶片，每个具有TEOS帽的多个晶体管栅极和沿着每个栅极的一对氮化物间隔物，多个 每个接触晶片的导电插塞和覆盖晶体管栅极并接触有源区的BPSG层。 BPSG层的一部分被蚀刻，从而暴露TEOS帽。 完成蚀刻后，BPSG层的一部分保留在有源区上。 随后，去除TEOS帽的一部分以暴露晶体管栅极，同时形成钛硅化物层以接触晶体管栅极和插塞。 还描述了由本发明方法产生的创造性结构。

公开(公告)号：US07030499B2

公开(公告)日：2006-04-18

申请号：US10999769

申请日：2004-11-29

申请人： Michael J. Hermes

发明人： Michael J. Hermes

IPC分类号： H01L23/48

CPC分类号： H01L21/76831 ,  H01L21/31116 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10891

摘要： The invention includes methods of forming openings extending through electrically insulative layers to electrically conductive materials. In an exemplary aspect, a substrate is provided which supports a stack and an electrical node. The stack comprises an electrically insulative cap over an electrically conductive material. An electrically insulative layer is formed over the stack and over the electrical node. A first etch is utilized to etch through the electrically insulative layer to the electrical node and to the electrically insulative cap. The first etch etches partially into the electrically insulative cap but does not etch entirely through the electrically insulative cap. A second etch is utilized after the first etch to etch entirely through the electrically insulative cap to the electrically conductive material of the stack.

摘要翻译： 本发明包括形成通过电绝缘层延伸到导电材料的开口的方法。 在示例性方面，提供了支撑堆叠和电节点的衬底。 叠层包括导电材料上的电绝缘帽。 电绝缘层形成在堆叠上并在电节点上方。 利用第一蚀刻将电绝缘层蚀刻到电节点和电绝缘帽。 第一蚀刻部分地蚀刻到电绝缘帽中，但是不完全通过电绝缘帽蚀刻。 在第一次蚀刻之后利用第二次蚀刻，以完全通过电绝缘帽蚀刻到叠层的导电材料。

公开(公告)号：US06828238B1

公开(公告)日：2004-12-07

申请号：US10454303

申请日：2003-06-03

申请人： Michael J. Hermes

发明人： Michael J. Hermes

IPC分类号： H01L21311

CPC分类号： H01L21/76831 ,  H01L21/31116 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10891

摘要： The invention includes methods of forming openings extending through electrically insulative layers to electrically conductive materials. In an exemplary aspect, a substrate is provided which supports a stack and an electrical node. The stack comprises an electrically insulative cap over an electrically conductive material. An electrically insulative layer is formed over the stack and over the electrical node. A first etch is utilized to etch through the electrically insulative layer to the electrical node and to the electrically insulative cap. The first etch etches partially into the electrically insulative cap but does not etch entirely through the electrically insulative cap. A second etch is utilized after the first etch to etch entirely through the electrically insulative cap to the electrically conductive material of the stack.

摘要翻译： 本发明包括形成通过电绝缘层延伸到导电材料的开口的方法。 在示例性方面，提供了支撑堆叠和电节点的衬底。 叠层包括导电材料上的电绝缘帽。 电绝缘层形成在堆叠上并在电节点上方。 利用第一蚀刻将电绝缘层蚀刻到电节点和电绝缘帽。 第一蚀刻部分地蚀刻到电绝缘帽中，但是不完全通过电绝缘帽蚀刻。 在第一次蚀刻之后利用第二次蚀刻，以完全通过电绝缘帽蚀刻到叠层的导电材料。

公开(公告)号：US06977418B2

公开(公告)日：2005-12-20

申请号：US10305465

申请日：2002-11-26

申请人： Michael J. Hermes ,  Kunal R. Parekh

发明人： Michael J. Hermes ,  Kunal R. Parekh

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L33/191

CPC分类号： H01L21/76897 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823475

摘要： A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along each gate, a plurality of conductive plugs each contacting the wafer, and a BPSG layer overlying the transistor gates and contacting the active area. A portion of the BPSG layer is etched thereby exposing the TEOS caps. A portion of the BPSG layer remains on the active area after completion of the etch. Subsequently, a portion of the TEOS caps are removed to expose the transistor gates and a titanium silicide layer is formed simultaneously to contact the transistor gates and the plugs. An inventive structure resulting from the inventive process is also described.

摘要翻译： 一种用于形成半导体器件的工艺包括以下步骤：提供半导体衬底组件，其包括其中形成有有效区的半导体晶片，每个具有TEOS帽的多个晶体管栅极和沿着每个栅极的一对氮化物间隔物，多个 每个接触晶片的导电插塞和覆盖晶体管栅极并接触有源区的BPSG层。 BPSG层的一部分被蚀刻，从而暴露TEOS帽。 完成蚀刻后，BPSG层的一部分保留在有源区上。 随后，去除TEOS帽的一部分以暴露晶体管栅极，同时形成钛硅化物层以接触晶体管栅极和插塞。 还描述了由本发明方法产生的创造性结构。

公开(公告)号：US06486060B2

公开(公告)日：2002-11-26

申请号：US09146639

申请日：1998-09-03

申请人： Michael J. Hermes ,  Kunal R. Parekh

发明人： Michael J. Hermes ,  Kunal R. Parekh

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823475

摘要： A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along each gate, a plurality of conductive plugs each contacting the wafer, and a BPSG layer overlying the transistor gates and contacting the active area. A portion of the BPSG layer is etched thereby exposing the TEOS caps. A portion of the BPSG layer remains on the active area after completion of the etch. Subsequently, a portion of the TEOS caps are removed to expose the transistor gates and a titanium silicide layer is formed simultaneously to contact the transistor gates and the plugs. An inventive structure resulting from the inventive process is also described.

摘要翻译： 一种用于形成半导体器件的方法包括以下步骤：提供半导体衬底组件，其包括其中形成有有效区的半导体晶片，每个具有TEOS帽的多个晶体管栅极和沿着每个栅极的一对氮化物间隔物，多个 每个接触晶片的导电插塞和覆盖晶体管栅极并接触有源区的BPSG层。 BPSG层的一部分被蚀刻，从而暴露TEOS帽。 完成蚀刻后，BPSG层的一部分保留在有源区上。 随后，去除TEOS帽的一部分以暴露晶体管栅极，同时形成钛硅化物层以接触晶体管栅极和插塞。 还描述了由本发明方法产生的创造性结构。