发明授权
US07358598B2 Process for fabricating a semiconductor package and semiconductor package with leadframe
有权
用于制造具有引线框的半导体封装和半导体封装的工艺
- 专利标题: Process for fabricating a semiconductor package and semiconductor package with leadframe
- 专利标题(中): 用于制造具有引线框的半导体封装和半导体封装的工艺
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申请号: US10827612申请日: 2004-04-19
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公开(公告)号: US07358598B2公开(公告)日: 2008-04-15
- 发明人: Jean-Luc Diot , Jerome Teysseyre
- 申请人: Jean-Luc Diot , Jerome Teysseyre
- 申请人地址: FR Montrouge
- 专利权人: STMicroelectronics S.A.
- 当前专利权人: STMicroelectronics S.A.
- 当前专利权人地址: FR Montrouge
- 代理机构: Gardere Wynne Sewell LLP
- 优先权: FR0305263 20030429
- 主分类号: H01L23/495
- IPC分类号: H01L23/495
摘要:
A semiconductor package includes a flat metal leadframe including spaced apart portions, at least some of which constitute electrical connection leads. A filling material fills the spaces that separate the spaced apart portions of the leadframe to form a plate before fastening an integrated circuit chip to the front of the leadframe. Electrical connections are made between the chip and the electrical connection leads. The chip is then encapsulated on the front of the leadframe using a formed or attached encapsulant.
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