Invention Grant
- Patent Title: High electrical performance semiconductor package
- Patent Title (中): 高电性能半导体封装
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Application No.: US10974376Application Date: 2004-10-26
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Publication No.: US07361846B2Publication Date: 2008-04-22
- Inventor: Wen-Jung Chiang , Chien-Te Chen , Yu-Po Wang
- Applicant: Wen-Jung Chiang , Chien-Te Chen , Yu-Po Wang
- Applicant Address: TW
- Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee Address: TW
- Agency: Edwards Angell Palmer & Dodge LLP
- Agent Peter F. Corless; Steven M. Jensen
- Priority: TW93113299A 20040512
- Main IPC: H05K1/16
- IPC: H05K1/16

Abstract:
A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.
Public/Granted literature
- US20050253253A1 High electrical performance semiconductor package Public/Granted day:2005-11-17
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