公开(公告)号：US20090020323A1

公开(公告)日：2009-01-22

申请号：US12218891

申请日：2008-07-18

申请人： Chien-Te Chen ,  Ke-Chuan Yang ,  Hung-Ming Chang

发明人： Chien-Te Chen ,  Ke-Chuan Yang ,  Hung-Ming Chang

IPC分类号： H05K1/09 ,  H05K3/10

CPC分类号： H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/114 ,  H05K3/108 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09436 ,  H05K2203/025 ,  H05K2203/0733 ,  Y10T29/49149 ,  H01L2924/00

摘要： A circuit board structure and a method for fabricating the same are disclosed, including providing a core board having conductive traces and solder pads respectively formed thereon, wherein width of the solder pads corresponds to that of the conductive traces, and pitch between adjacent solder pads is made wide enough to allow multiple conductive traces to pass through; forming on the core board an insulating layer with openings for exposing the solder pads therefrom; forming on the insulating layer a plurality of extending pads electrically connected to the solder pads respectively, wherein the projection area of the extending pads is larger than that of the corresponding solder pads and covers conductive traces adjacent to the corresponding solder pads. Thus, more conductive traces are allowed to pass between adjacent solder pads and meanwhile, the extending pads provide an effective solder ball wetting area for achieving good solder joints and sufficient height after collapse.

摘要翻译： 公开了一种电路板结构及其制造方法，包括提供具有分别形成在其上的导电迹线和焊盘的芯板，其中焊盘的宽度对应于导电迹线的宽度，相邻焊盘之间的间距是 足够宽以允许多个导电迹线通过; 在所述芯板上形成具有用于从其露出焊盘的开口的绝缘层; 在所述绝缘层上形成分别电连接到所述焊盘的多个延伸焊盘，其中所述延伸焊盘的所述投影区域大于相应焊接焊盘的所述投影区域并且覆盖与相应焊盘相邻的导电迹线。 因此，允许更多的导电迹线在相邻焊盘之间通过，同时，延伸焊盘提供有效的焊球润湿区域，以实现良好的焊点和崩溃后的足够的高度。

公开(公告)号：US20080277144A1

公开(公告)日：2008-11-13

申请号：US12176562

申请日：2008-07-21

申请人： Chien-Te Chen ,  Chih-Hao Chang

发明人： Chien-Te Chen ,  Chih-Hao Chang

IPC分类号： H05K1/00 ,  H05K3/20

CPC分类号： H05K1/0269 ,  H05K3/0052 ,  H05K3/242 ,  H05K3/403 ,  H05K3/4602 ,  H05K2201/0919 ,  H05K2201/09781 ,  H05K2203/163 ,  H05K2203/175 ,  Y10T29/49128

摘要： A circuit board with a quality-indicator mark and a method for indicating quality of the circuit board. The circuit board includes a plurality of circuit board units. A plating bus is formed around each circuit board unit and extended to form a plating trace in an inner-layer circuit structure of each circuit board unit. The inner-layer circuit structure is inspected in quality to maintain or break connection between the plating trace and plating bus if the quality is good or not. At least one circuit structure is formed on the inner-layer circuit structure and electrically connected to the plating trace to form a conductive mark on each circuit board unit. A metal protection layer is formed on the at least one circuit structure via the plating bus, and the conductive mark with the metal protection layer indicates that the inner-layer circuit structure of the circuit board unit is good.

摘要翻译： 具有质量指示标记的电路板和用于指示电路板的质量的方法。 电路板包括多个电路板单元。 在每个电路板单元周围形成电镀母线，并延伸以在每个电路板单元的内层电路结构中形成电镀痕迹。 如果质量好，内层电路结构的质量将被检查以维持或断开电镀痕迹和电镀母线之间的连接。 在内层电路结构上形成至少一个电路结构，并电连接到电镀迹线，以在每个电路板单元上形成导电标记。 金属保护层通过电镀母线形成在至少一个电路结构上，金属保护层的导电标记表示电路板单元的内层电路结构良好。

公开(公告)号：US07402755B2

公开(公告)日：2008-07-22

申请号：US10935870

申请日：2004-09-07

申请人： Chien-Te Chen ,  Chih-Hao Chang

发明人： Chien-Te Chen ,  Chih-Hao Chang

IPC分类号： H05K1/00

CPC分类号： H05K1/0269 ,  H05K3/0052 ,  H05K3/242 ,  H05K3/403 ,  H05K3/4602 ,  H05K2201/0919 ,  H05K2201/09781 ,  H05K2203/163 ,  H05K2203/175 ,  Y10T29/49128

摘要： A circuit board with a quality-indicator mark and a method for indicating quality of the circuit board. The circuit board includes a plurality of circuit board units. A plating bus is formed around each circuit board unit and extended to form a plating trace in an inner-layer circuit structure of each circuit board unit. The inner-layer circuit structure is inspected in quality to maintain or break connection between the plating trace and plating bus if the quality is good or not. At least one circuit structure is formed on the inner-layer circuit structure and electrically connected to the plating trace to form a conductive mark on each circuit board unit. A metal protection layer is formed on the at least one circuit structure via the plating bus, and the conductive mark with the metal protection layer indicates that the inner-layer circuit structure of the circuit board unit is good.

摘要翻译： 具有质量指示标记的电路板和用于指示电路板的质量的方法。 电路板包括多个电路板单元。 在每个电路板单元周围形成电镀母线，并延伸以在每个电路板单元的内层电路结构中形成电镀痕迹。 如果质量好，内层电路结构的质量将被检查以维持或断开电镀痕迹和电镀母线之间的连接。 在内层电路结构上形成至少一个电路结构，并电连接到电镀迹线，以在每个电路板单元上形成导电标记。 金属保护层通过电镀母线形成在至少一个电路结构上，金属保护层的导电标记表示电路板单元的内层电路结构良好。

公开(公告)号：US07361846B2

公开(公告)日：2008-04-22

申请号：US10974376

申请日：2004-10-26

申请人： Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

发明人： Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

IPC分类号： H05K1/16

CPC分类号： H01L23/49838 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.

摘要翻译： 提出了一种高性能半导体封装。 提供具有第一表面，相对的第二表面和用于将第一表面电连接到第二表面的导电通孔的载体。 芯片附接到载体的第一表面。 多个通孔焊盘周边设置在载体的第一表面上并电连接到通孔。 多个导电区域设置在载体的第二表面上并电连接到通孔。 多个指状物设置在芯片周围，并通过形成在载体的第一表面上的导电迹线电连接到通孔焊盘。 多个接合线将芯片电连接到手指。 用于传输差分对信号的导线的长度基本相等，用于发送差分对信号的迹线的长度基本相等。

公开(公告)号：US20060125075A1

公开(公告)日：2006-06-15

申请号：US11059143

申请日：2005-02-15

申请人： Yu-Lin Liao ,  Chien-Te Chen

发明人： Yu-Lin Liao ,  Chien-Te Chen

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H05K3/242 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49894 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K3/0052 ,  H05K3/28 ,  H05K3/284 ,  H05K2201/09781 ,  H05K2201/0989 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00012

摘要： A flash preventing substrate and a method for fabricating the same are proposed. A core defined with a plurality of substrate units is prepared. A circuit patterning process is performed to form circuit structures on the core corresponding to the substrate units, plating buses between the adjacent substrate units and electrically connected to the circuit structures, and a molding ring surrounding all the substrate units. The molding ring is located at a position predetermined for contacting the substrate with a mold. A solder mask layer covers the circuit structures, the plating buses and the molding ring, and is formed with a plurality of openings therein, such that predetermined portions of the circuit structures are exposed via the openings and serve as electrical input/output connections. During a molding process, the mold can tightly abut against the solder mask layer covering the molding ring to prevent outward flashes of an encapsulating material.

公开(公告)号：US06700204B2

公开(公告)日：2004-03-02

申请号：US10038732

申请日：2002-01-02

申请人： Chien-Ping Huang ,  Chien-Te Chen

发明人： Chien-Ping Huang ,  Chien-Te Chen

IPC分类号： H01R2348

CPC分类号： H05K3/3442 ,  H05K1/111 ,  H05K3/28 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T428/24917

摘要： A substrate for accommodating a passive component is proposed, including a core layer defined with a chip attach area and a trace forming area surrounding the chip attach area, with a solder mask layer being applied on the trace forming area. At least a pair of solder pads are formed on the trace forming area, and partly exposed to outside of the solder mask layer. The solder pads are each formed at a central position with an recess, allowing the core layer to be partly exposed through the recesses of the solder pads. For bonding a passive component to the solder pads, solder paste soldered on the solder pads forms a recessed top surface due to surface tension of the solder paste, and generates a downward and convergent dragging force for properly positioning the passive component on the solder pads without producing shifting or tombstone effect.

摘要翻译： 提出了一种用于容纳无源部件的基板，包括由芯片附着区域限定的芯层和围绕芯片附着区域的迹线形成区域，在迹线形成区域上施加有阻焊层。 在迹线形成区域上形成至少一对焊盘，并且部分地暴露于焊料掩模层的外部。 焊盘各自形成在具有凹部的中心位置，允许芯层通过焊盘的凹部部分露出。 为了将无源部件焊接到焊盘，由于焊膏的表面张力焊接在焊盘上的焊膏形成凹陷的顶部表面，并且产生向下且会聚的拖曳力，以将无源部件适当地定位在焊盘上，而无需 产生转移或墓碑效应。

公开(公告)号：US06449169B1

公开(公告)日：2002-09-10

申请号：US09796316

申请日：2001-02-28

申请人： Tzong-Da Ho ,  Chih-Chin Liao ,  Chien-Te Chen

发明人： Tzong-Da Ho ,  Chih-Chin Liao ,  Chien-Te Chen

IPC分类号： H05K118

CPC分类号： H01L24/49 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： A BGA (Ball Grid Array) package is proposed, which is characterized by the provision of an interdigitated power/ground ring layout scheme. By this layout scheme, the power ring and the ground ring are each formed with a line portion and a plurality of toothed portions; with the toothed portions of the power ring being are interdigitated with the toothed portions of the ground ring. Moreover, the power/ground vias are all connected to the toothed portions of the power ring and the ground ring, thereby leaving the line portions of the power ring and the ground ring unoccupied by the power/ground vias, allowing the routability of power/ground wires to be higher than the prior art. Moreover, solder bask is formed in such a manner as to cover all the toothed portions of the ground ring, so that power wires can be prevented from being short-circuited to the ground ring due to sagging. Further, the toothed portions of the power ring and the ground ring are large in area, whereby two or more power vias or ground vias can be gathered together to increase the overall electrical performance, and whereby the packaged chip can be increased in heat-dissipation efficiency.

摘要翻译： 提出了一种BGA（球栅阵列）封装，其特征在于提供交叉电源/接地环布局方案。 通过该布置方案，功率环和接地环各自形成有线部分和多个齿形部分; 电源环的齿形部分与接地环的齿形部分交错。 此外，电源/接地通孔都连接到电源环和接地环的齿形部分，从而使电源环和接地环的线路部分不被电源/接地通孔占据，从而允许电力/ 接地线高于现有技术。 此外，焊盘以覆盖接地环的所有齿部的方式形成，从而可以防止电源线由于下垂而与接地环短路。 此外，电源环和接地环的齿形部分面积大，由此可以将两个或更多个电源通孔或接地通孔聚集在一起以增加整体电气性能，从而可以增加封装芯片的散热能力 效率。

公开(公告)号：US20060049516A1

公开(公告)日：2006-03-09

申请号：US11145318

申请日：2005-06-03

申请人： Yu-Po Wang ,  Chiang-Cheng Chang ,  Chien-Te Chen

发明人： Yu-Po Wang ,  Chiang-Cheng Chang ,  Chien-Te Chen

IPC分类号： H01L23/48

CPC分类号： H05K3/243 ,  H01L21/563 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/064 ,  H05K3/3452 ,  H05K2201/09845 ,  H05K2203/0542 ,  Y02P70/611 ,  H01L2924/00

摘要： A nickel/gold (Ni/Au) pad structure of a semiconductor package and a fabrication method thereof are provided. The fabrication method includes preparing a core layer; forming a conductive trace layer on the core layer; patterning the conductive trace layer to form at least one pad of the conductive trace layer; applying a conductive layer; forming a photoresist layer to define a predetermined plating region on the pad, wherein the predetermined plating region is smaller in area than the pad; forming a Ni/Au layer on the predetermined plating region; removing the photoresist layer and etching away the conductive layer; and applying a solder mask layer and forming at least one opening in the solder mask layer to expose the pad, wherein the opening is larger in area than the Ni/Au layer. The Ni/Au pad structure fabricated by the above method can prevent a solder extrusion effect incurred in the conventional technology.

摘要翻译： 提供半导体封装的镍/金（Ni / Au）焊盘结构及其制造方法。 制造方法包括制备芯层; 在芯层上形成导电迹线层; 图案化导电迹线层以形成至少一个导电迹线层的焊盘; 施加导电层; 形成光致抗蚀剂层以在所述焊盘上限定预定的镀覆区域，其中所述预定电镀区域的面积小于所述焊盘; 在预定的电镀区上形成Ni / Au层; 去除光致抗蚀剂层并蚀刻掉导电层; 以及施加焊接掩模层并在所述焊料掩模层中形成至少一个开口以露出所述焊盘，其中所述开口面积大于所述Ni / Au层。 通过上述方法制造的Ni / Au焊盘结构可以防止传统技术中引起的焊料挤出效应。

公开(公告)号：US08772647B1

公开(公告)日：2014-07-08

申请号：US13443508

申请日：2012-04-10

申请人： Chien Te Chen

发明人： Chien Te Chen

IPC分类号： H01K3/10 ,  H05K1/11

CPC分类号： H05K1/113 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0959 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： Methods for the formation of single-cap VIPs in a substrate are described herein. The methods may include initially providing a substrate having a first and a second side, the first side being opposite of the second side. A via may then be constructed in the substrate, the via being formed within a via hole that extends from the first side to the second side of the substrate, the formed via having a first end located at the first side of the substrate, and a second end opposite the first end located at the second side of the substrate. A selective deposition may be performed of a conductive material on the second end of the via to form a conductive pad directly on the via on the second side of the substrate without depositing the conductive material onto the first side of the substrate.

摘要翻译： 本文描述了在底物中形成单帽VIP的方法。 所述方法可以包括最初提供具有第一和第二侧的衬底，第一侧与第二侧相对。 然后可以在衬底中构造通孔，所述通孔形成在从衬底的第一侧延伸到第二侧的通孔中，所形成的通孔具有位于衬底的第一侧的第一端，以及 第二端相对于位于基板的第二侧的第一端。 可以在通孔的第二端上执行导电材料的选择性沉积，以在衬底的第二侧上的通孔上直接形成导电焊盘，而不将导电材料沉积到衬底的第一侧上。

公开(公告)号：US20050253253A1

公开(公告)日：2005-11-17

申请号：US10974376

申请日：2004-10-26

申请人： Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

发明人： Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

IPC分类号： H01L23/10 ,  H01L23/367 ,  H01L23/498

CPC分类号： H01L23/49838 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.

摘要翻译： 提出了一种高性能半导体封装。 提供具有第一表面，相对的第二表面和用于将第一表面电连接到第二表面的导电通孔的载体。 芯片附接到载体的第一表面。 多个通孔焊盘周边设置在载体的第一表面上并电连接到通孔。 多个导电区域设置在载体的第二表面上并电连接到通孔。 多个指状物设置在芯片周围，并通过形成在载体的第一表面上的导电迹线电连接到通孔焊盘。 多个接合线将芯片电连接到手指。 用于传输差分对信号的导线的长度基本相等，用于发送差分对信号的迹线的长度基本相等。