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    High electrical performance semiconductor package
    1.
    发明授权
    High electrical performance semiconductor package 有权
    高电性能半导体封装

    公开(公告)号：US07361846B2

    公开(公告)日：2008-04-22

    申请号：US10974376

    申请日：2004-10-26

    申请人： Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

    发明人： Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

    IPC分类号： H05K1/16

    CPC分类号： H01L23/49838 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.

    摘要翻译： 提出了一种高性能半导体封装。 提供具有第一表面，相对的第二表面和用于将第一表面电连接到第二表面的导电通孔的载体。 芯片附接到载体的第一表面。 多个通孔焊盘周边设置在载体的第一表面上并电连接到通孔。 多个导电区域设置在载体的第二表面上并电连接到通孔。 多个指状物设置在芯片周围，并通过形成在载体的第一表面上的导电迹线电连接到通孔焊盘。 多个接合线将芯片电连接到手指。 用于传输差分对信号的导线的长度基本相等，用于发送差分对信号的迹线的长度基本相等。

    High electrical performance semiconductor package
    2.
    发明申请
    High electrical performance semiconductor package 有权
    高电性能半导体封装

    公开(公告)号：US20050253253A1

    公开(公告)日：2005-11-17

    申请号：US10974376

    申请日：2004-10-26

    申请人： Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

    发明人： Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

    IPC分类号： H01L23/10 ,  H01L23/367 ,  H01L23/498

    CPC分类号： H01L23/49838 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.

    摘要翻译： 提出了一种高性能半导体封装。 提供具有第一表面，相对的第二表面和用于将第一表面电连接到第二表面的导电通孔的载体。 芯片附接到载体的第一表面。 多个通孔焊盘周边设置在载体的第一表面上并电连接到通孔。 多个导电区域设置在载体的第二表面上并电连接到通孔。 多个指状物设置在芯片周围，并通过形成在载体的第一表面上的导电迹线电连接到通孔焊盘。 多个接合线将芯片电连接到手指。 用于传输差分对信号的导线的长度基本相等，用于发送差分对信号的迹线的长度基本相等。

    Semiconductor package substrate
    3.
    发明授权
    Semiconductor package substrate 有权
    半导体封装基板

    公开(公告)号：US07732913B2

    公开(公告)日：2010-06-08

    申请号：US11701767

    申请日：2007-02-02

    申请人： Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    发明人： Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    IPC分类号： H01L23/04

    CPC分类号： H01L23/49827 ,  H01L23/64 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718 ,  H01L2924/00

    摘要： A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

    摘要翻译： 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

    Semiconductor package substrate
    4.
    发明申请
    Semiconductor package substrate 有权
    半导体封装基板

    公开(公告)号：US20070273026A1

    公开(公告)日：2007-11-29

    申请号：US11701767

    申请日：2007-02-02

    申请人： Hsieh-Tsung Tien ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    发明人： Hsieh-Tsung Tien ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    IPC分类号： H01L23/488

    CPC分类号： H01L23/49827 ,  H01L23/64 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718 ,  H01L2924/00

    摘要： A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

    摘要翻译： 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

    Nickel/gold pad structure of semiconductor package and fabrication method thereof
    6.
    发明申请
    Nickel/gold pad structure of semiconductor package and fabrication method thereof 审中-公开
    半导体封装的镍/金焊盘结构及其制造方法

    公开(公告)号：US20060049516A1

    公开(公告)日：2006-03-09

    申请号：US11145318

    申请日：2005-06-03

    申请人： Yu-Po Wang ,  Chiang-Cheng Chang ,  Chien-Te Chen

    发明人： Yu-Po Wang ,  Chiang-Cheng Chang ,  Chien-Te Chen

    IPC分类号： H01L23/48

    CPC分类号： H05K3/243 ,  H01L21/563 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/064 ,  H05K3/3452 ,  H05K2201/09845 ,  H05K2203/0542 ,  Y02P70/611 ,  H01L2924/00

    摘要： A nickel/gold (Ni/Au) pad structure of a semiconductor package and a fabrication method thereof are provided. The fabrication method includes preparing a core layer; forming a conductive trace layer on the core layer; patterning the conductive trace layer to form at least one pad of the conductive trace layer; applying a conductive layer; forming a photoresist layer to define a predetermined plating region on the pad, wherein the predetermined plating region is smaller in area than the pad; forming a Ni/Au layer on the predetermined plating region; removing the photoresist layer and etching away the conductive layer; and applying a solder mask layer and forming at least one opening in the solder mask layer to expose the pad, wherein the opening is larger in area than the Ni/Au layer. The Ni/Au pad structure fabricated by the above method can prevent a solder extrusion effect incurred in the conventional technology.

    摘要翻译： 提供半导体封装的镍/金（Ni / Au）焊盘结构及其制造方法。 制造方法包括制备芯层; 在芯层上形成导电迹线层; 图案化导电迹线层以形成至少一个导电迹线层的焊盘; 施加导电层; 形成光致抗蚀剂层以在所述焊盘上限定预定的镀覆区域，其中所述预定电镀区域的面积小于所述焊盘; 在预定的电镀区上形成Ni / Au层; 去除光致抗蚀剂层并蚀刻掉导电层; 以及施加焊接掩模层并在所述焊料掩模层中形成至少一个开口以露出所述焊盘，其中所述开口面积大于所述Ni / Au层。 通过上述方法制造的Ni / Au焊盘结构可以防止传统技术中引起的焊料挤出效应。

    Semiconductor device and fabrication method thereof
    9.
    发明申请
    Semiconductor device and fabrication method thereof 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20070164386A1

    公开(公告)日：2007-07-19

    申请号：US11648045

    申请日：2006-12-28

    申请人： Cheng-Yi Chang ,  Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    发明人： Cheng-Yi Chang ,  Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    IPC分类号： H01L31/0203 ,  H01L21/56

    CPC分类号： H01L27/14687 ,  H01L24/97 ,  H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2224/85 ,  H01L2924/00014

    摘要： A semiconductor device and the fabrication method thereof are provided. The fabrication method includes providing a substrate module plate having a plurality of substrates; attaching at least one sensor chip to each of the substrates of the substrate module plate; electrically connecting each of the sensor chips to each of the substrates through bonding wires; forming an insulating layer between each sensor chip on the substrate module plate, wherein the height of the insulating layers are not greater than the thickness of the sensor chips so as to prevent flash from the insulating layers from contaminating the sensor chips; forming an adhesive lip on the insulating layer or forming a second insulating layer followed by forming the adhesive layer, wherein the adhesive layer or the second insulating layer is higher than the highest loop-height of the bonding wires; adhering a light transmitting cover to each adhesive layer to cover the sensor chip; and cutting the substrate module plate to separate the substrates to form a plurality of semiconductor devices each integrated with at least one sensor chip. As the adhesive layers are not in contact with the bonding wires, the problems of damaging or breaking the bonding wires can be prevented in the process of adhering the light transmitting cover.

    摘要翻译： 提供半导体器件及其制造方法。 该制造方法包括提供具有多个基板的基板模块板; 将至少一个传感器芯片附接到所述基板模块板的每个基板; 通过接合线将每个传感器芯片电连接到每个基板; 在衬底模块板上的每个传感器芯片之间形成绝缘层，其中绝缘层的高度不大于传感器芯片的厚度，以防止来自绝缘层的闪光污染传感器芯片; 在所述绝缘层上形成粘合剂唇缘或形成第二绝缘层，接着形成所述粘合剂层，其中所述粘合剂层或所述第二绝缘层高于所述接合线的最高环高度; 将透光盖粘附到每个粘合剂层以覆盖传感器芯片; 以及切割所述基板模块板以分离所述基板以形成多个半导体器件，每个半导体器件与至少一个传感器芯片集成。 由于粘合层不与接合线接触，所以在粘接透光罩的过程中可以防止损坏或断裂接合线的问题。