Invention Grant
- Patent Title: Integrated circuit selective scaling
- Patent Title (中): 集成电路选择性缩放
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Application No.: US10711959Application Date: 2004-10-15
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Publication No.: US07363601B2Publication Date: 2008-04-22
- Inventor: Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani R. Narayan , Stephen L. Runyon , Robert F. Walker
- Applicant: Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani R. Narayan , Stephen L. Runyon , Robert F. Walker
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick & D'Alessandro LLC
- Agent Richard M. Kotulak
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.
Public/Granted literature
- US20060085768A1 INTEGRATED CIRCUIT SELECTIVE SCALING Public/Granted day:2006-04-20
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