公开(公告)号：US07568173B2

公开(公告)日：2009-07-28

申请号：US11762832

申请日：2007-06-14

申请人： Veit Gernhoefer ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani Narayan ,  Stephen L. Runyon ,  Leon J. Sigal ,  Robert F. Walker ,  Pieter J. Woeltgens ,  Xiaoyun K. Wu ,  Xin Yuan

发明人： Veit Gernhoefer ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani Narayan ,  Stephen L. Runyon ,  Leon J. Sigal ,  Robert F. Walker ,  Pieter J. Woeltgens ,  Xiaoyun K. Wu ,  Xin Yuan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.

摘要翻译： 公开了独立迁移分层设计的方法。 一种用于迁移集成电路中的宏的方法，包括：确定宏中的基本单元与宏之间的接口策略，所述基本单元包括接口策略中涉及的接口元素; 基于接口策略相对于宏独立地移动基站; 最初缩放宏; 将迁移的基本单元交换到宏中; 并使初始缩放的宏的内容合法化。

公开(公告)号：US5212662A

公开(公告)日：1993-05-18

申请号：US580892

申请日：1990-09-11

申请人： Daniel Cocanougher ,  Robert K. Montoye ,  Myhong Nguyenphu ,  Stephen L. Runyon

发明人： Daniel Cocanougher ,  Robert K. Montoye ,  Myhong Nguyenphu ,  Stephen L. Runyon

IPC分类号： G06F7/544 ,  G06F7/57

CPC分类号： G06F7/5443 ,  G06F7/483 ,  G06F7/49947

摘要： A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.

摘要翻译： 提供一种用于执行浮点算术运算的处理器，其包括对第一周期中的一组操作数执行第一浮点算术运算的电路和对操作数的第二浮点运算和第一浮点运算结果 在第二周期的算术运算。 提供一种控制电路，用于在第三个周期内将第二浮动操作的结果传送到第一浮点运算，用于在下一个连续循环中进行第一浮点运算，同时舍入第二浮点运算的结果。

公开(公告)号：US4999802A

公开(公告)日：1991-03-12

申请号：US297781

申请日：1989-01-13

申请人： Daniel Cocanougher ,  Robert K. Montoye ,  Myhong Nguyenphu ,  Stephen L. Runyon

发明人： Daniel Cocanougher ,  Robert K. Montoye ,  Myhong Nguyenphu ,  Stephen L. Runyon

IPC分类号： G06F7/38 ,  G06F7/485 ,  G06F7/487 ,  G06F7/527 ,  G06F7/544 ,  G06F7/57

CPC分类号： G06F9/3889 ,  G06F7/483 ,  G06F7/5443 ,  G06F7/49947

摘要： A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.

公开(公告)号：US07882463B2

公开(公告)日：2011-02-01

申请号：US12035572

申请日：2008-02-22

申请人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

发明人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.

摘要翻译： 本发明包括通过以下方式选择性地缩放集成电路（IC）设计的解决方案：层，区域或单元，或它们的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了使设计人员提高产量的需要。

公开(公告)号：US07537997B2

公开(公告)日：2009-05-26

申请号：US12114965

申请日：2008-05-05

申请人： Stephen L. Runyon ,  Scott Stiffler

发明人： Stephen L. Runyon ,  Scott Stiffler

IPC分类号： H01L21/8234

CPC分类号： H01L29/7833 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7843

摘要： Mechanisms for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point.

摘要翻译： 提供了确保电路迁移到未来技术同时最小化制造成本和维持或提高功率效率的机制。 在将应力感应层施加到集成电路之前，将掩模层引入到集成电路的部分。 在示例性实施例中，将拉伸或压缩膜施加到集成电路芯片上的器件，但是从要进行修改的器件中移除。 此后，将拉伸或压缩应变层施加到其膜去除的装置上。 然后可以使用另外的掩模层来实现光晕或井注入，以松弛未被掩模层保护的器件上的应变。 以这种方式，无保护设备的电流减少到原来的目标设计点。

公开(公告)号：US20080148210A1

公开(公告)日：2008-06-19

申请号：US12035572

申请日：2008-02-22

申请人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

发明人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.

摘要翻译： 本发明包括通过以下方式选择性地缩放集成电路（IC）设计的解决方案：层，区域或单元，或它们的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了使设计人员提高产量的需要。

公开(公告)号：US07865848B2

公开(公告)日：2011-01-04

申请号：US11846017

申请日：2007-08-28

申请人： Veit Gernhoefer ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen L. Runyon ,  Robert F. Walker ,  Bruce C. Wheeler

发明人： Veit Gernhoefer ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen L. Runyon ,  Robert F. Walker ,  Bruce C. Wheeler

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.

摘要翻译： 包含参数化单元格的布局优化方法包括读取包含参数化单元格的物理设计，为给定参数化单元格的每个使用创建新版本。 该方法通过根据期望的目标将参数分配给参数化单元的参数来优化每个新版本的参数化单元的物理设计形状。 然后，该方法更新参数化单元的每个新版本的参数，并用具有更新参数的参数化单元的实例替换参数化单元的每个新版本。 该方法可以基于与参数相关的约束来可选地调整物理设计形状。

公开(公告)号：US07627836B2

公开(公告)日：2009-12-01

申请号：US11164044

申请日：2005-11-08

申请人： James A. Culp ,  Lars W. Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen L. Runyon ,  Patrick M. Williams

发明人： James A. Culp ,  Lars W. Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen L. Runyon ,  Patrick M. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

摘要翻译： 基于使用光学邻近校正技术的方法，在芯片制造之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。 附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为所选的关键设备制作掩码。

公开(公告)号：US20090064061A1

公开(公告)日：2009-03-05

申请号：US11846017

申请日：2007-08-28

申请人： Veit Gernhoefer ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen L. Runyon ,  Robert F. Walker ,  Bruce C. Wheeler

发明人： Veit Gernhoefer ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen L. Runyon ,  Robert F. Walker ,  Bruce C. Wheeler

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.

摘要翻译： 包含参数化单元格的布局优化方法包括读取包含参数化单元格的物理设计，为给定参数化单元格的每个使用创建新版本。 该方法通过根据期望的目标将参数分配给参数化单元的参数来优化每个新版本的参数化单元的物理设计形状。 然后，该方法更新参数化单元的每个新版本的参数，并用具有更新参数的参数化单元的实例替换参数化单元的每个新版本。 该方法可以基于与参数相关的约束来可选地调整物理设计形状。

公开(公告)号：US20080203489A1

公开(公告)日：2008-08-28

申请号：US12114965

申请日：2008-05-05

申请人： Stephen L. Runyon ,  Scott Stiffler

发明人： Stephen L. Runyon ,  Scott Stiffler

IPC分类号： H01L21/8234

CPC分类号： H01L29/7833 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7843

摘要： Mechanisms for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point.

摘要翻译： 提供了确保电路迁移到未来技术同时最小化制造成本和维持或提高功率效率的机制。 在将应力感应层施加到集成电路之前，将掩模层引入到集成电路的部分。 在示例性实施例中，将拉伸或压缩膜施加到集成电路芯片上的器件，但是从要进行修改的器件中移除。 此后，将拉伸或压缩应变层施加到其膜去除的装置上。 然后可以使用附加的掩模层来实现光晕或井注入，以松弛未被掩模层保护的器件上的应变。 以这种方式，无保护设备的电流减少到原来的目标设计点。