发明授权
US07372741B2 Nonvolatile memory apparatus having a processor and plural memories one or more of which is a nonvolatile memory having circuitry which performs an erase operation and an erase verify operation when the processor specifies the erase operation mode to the nonvolatile memory
失效
具有处理器和多个存储器的非易失性存储装置，其中一个或多个是具有执行擦除操作和擦除验证操作的电路的非易失性存储器，当处理器向非易失性存储器指定擦除操作模式时
- 专利标题： Nonvolatile memory apparatus having a processor and plural memories one or more of which is a nonvolatile memory having circuitry which performs an erase operation and an erase verify operation when the processor specifies the erase operation mode to the nonvolatile memory
- 专利标题（中）： 具有处理器和多个存储器的非易失性存储装置，其中一个或多个是具有执行擦除操作和擦除验证操作的电路的非易失性存储器，当处理器向非易失性存储器指定擦除操作模式时
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申请号： US11476745申请日： 2006-06-29
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公开(公告)号： US07372741B2公开(公告)日： 2008-05-13
- 发明人: Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
- 申请人： Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
- 申请人地址： JP Tokyo JP Tokyo
- 专利权人： Renesas Technology Corp.,Hitachi ULSI Systems Co., Ltd.
- 当前专利权人： Renesas Technology Corp.,Hitachi ULSI Systems Co., Ltd.
- 当前专利权人地址： JP Tokyo JP Tokyo
- 代理机构： Antonelli, Terry, Stout & Kraus, LLP.
- 优先权： JP1-27271 19890206; JP1-210262 19890815; JP1-243603 19890920; JP2-13614 19900125
- 主分类号： G11C11/34
- IPC分类号： G11C11/34
摘要：
A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation in the nonvolatile memory performs a threshold voltage moving operation and a verify operation, and the nonvolatile memory is capable of releasing the I/O bus during the erase operation to thereby allow accessing of other memories and/or system components. For example, during this erase operation, the Flash EEPROM is able to free the I/O data terminal such that the EEPROM becomes electrically isolated from the CPU. The CPU is then able to perform data processing by the system bus where information can then be transferred/received such as between other memories, e.g., ROM and RAM, and otherwise with the I/O port.
公开/授权文献
- US20060262605A1 Nonvolatile semiconductor memory device 公开/授权日：2006-11-23
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