公开(公告)号：US06747902B2

公开(公告)日：2004-06-08

申请号：US10176318

申请日：2002-06-21

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C1604

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： A nonvolatile memory apparatus contains plural memories, at least one of which is a nonvolatile memory, and a processing unit. Data input/output (I/O) terminals of the memories and processing unit are mutually coupled by a bus. When the nonvolatile memory is brought into an erasing mode by the processing unit, it becomes electrically isolated as a result of freeing the connection of the I/O terminal thereof during the erase operation. Accordingly, the processing unit is capable of accessing other memories via the bus where information can then be transferred/received between other memory devices and, otherwise, with the input/output port of the system. Control by the processing unit requires a relatively short time during which the erasing commencement is instructed so as to minimize interruption of the throughput capability of the system. Following the designation of an erasing mode, a data polling mode is designated.

摘要翻译： 非易失性存储装置包括多个存储器，其中至少一个是非易失性存储器，以及处理单元。 存储器和处理单元的数据输入/输出（I / O）端子通过总线相互耦合。 当非易失性存储器由处理单元进入擦除模式时，由于在擦除操作期间释放其I / O端子的连接，它变得电隔离。 因此，处理单元能够经由总线访问其他存储器，其中可以在其他存储器件之间传递/接收信息，否则可以与系统的输入/输出端口进行传送/接收。 处理单元的控制需要相对较短的时间，在该时间内指示擦除开始，以便最小化系统的吞吐量能力的中断。 指定擦除模式后，指定数据轮询模式。

公开(公告)号：US5844842A

公开(公告)日：1998-12-01

申请号：US249899

申请日：1994-05-26

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

公开(公告)号：US6157576A

公开(公告)日：2000-12-05

申请号：US393301

申请日：1999-09-10

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

摘要翻译： 在具有其中电可擦除非易失性存储元件以矩阵形式布置的存储器阵列的EEPROM中，包括擦除控制电路，其在执行擦除操作之后在对应的存储器单元上至少执行一次读出操作 根据外部提供的擦除操作指令。 擦除操作由内部擦除控制电路自动执行，同时响应于来自微处理器的指令，EEPROM与微处理器电隔离。 微处理器的控制只需要稍微短的时间段，在擦除操作期间EEPROM保留在系统中时，指令擦除开始。 在本发明的一个方面中，将Vcc电源施加到每个非易失性半导体存储单元的源极区域或漏极区域，并且将具有与Vcc电源的极性相反的极性的擦除电压施加到控制栅极 电极。 擦除电压被提供给设置在非易失性存储器件内的电压转换电路。 因此，可以通过Vcc单电源实现擦除操作。 此外，响应于每个存储元件的单独擦除速度，对于每个存储元件或每个集合存储元件单独控制集体擦除操作的实质端子。

公开(公告)号：US5781476A

公开(公告)日：1998-07-14

申请号：US456797

申请日：1995-06-01

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

公开(公告)号：US20060262605A1

公开(公告)日：2006-11-23

申请号：US11476745

申请日：2006-06-29

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C16/04

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation in the nonvolatile memory performs a threshold voltage moving operation and a verify operation, and the nonvolatile memory is capable of releasing the I/O bus during the erase operation to thereby allow accessing of other memories and/or system components. For example, during this erase operation, the Flash EEPROM is able to free the I/O data terminal such that the EEPROM becomes electrically isolated from the CPU. The CPU is then able to perform data processing by the system bus where information can then be transferred/received such as between other memories, e.g., ROM and RAM, and otherwise with the I/O port.

公开(公告)号：US07020028B2

公开(公告)日：2006-03-28

申请号：US10837984

申请日：2004-05-04

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C16/04

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.

公开(公告)号：US06259629B1

公开(公告)日：2001-07-10

申请号：US09425041

申请日：1999-10-19

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C1134

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

公开(公告)号：US06181600B2

公开(公告)日：2001-01-30

申请号：US09342225

申请日：1999-06-29

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C1134

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

摘要翻译： 在具有其中电可擦除非易失性存储元件以矩阵形式布置的存储器阵列的EEPROM中，包括擦除控制电路，其在执行擦除操作之后在对应的存储器单元上至少执行一次读出操作 根据外部提供的擦除操作指令。 擦除操作由内部擦除控制电路自动执行，同时响应于来自微处理器的指令，EEPROM与微处理器电隔离。 微处理器的控制只需要稍微短的时间段，在擦除操作期间EEPROM保留在系统中时，指令擦除开始。 在本发明的一个方面中，将Vcc电源施加到每个非易失性半导体存储单元的源极区域或漏极区域，并且将具有与Vcc电源的极性相反的极性的擦除电压施加到控制栅极 电极。 擦除电压被提供给设置在非易失性存储器件内的电压转换电路。 因此，可以通过Vcc单电源实现擦除操作。 此外，响应于每个存储元件的单独擦除速度，对于每个存储元件或每个集合存储元件单独控制集体擦除操作的实质端子。

公开(公告)号：US6016273A

公开(公告)日：2000-01-18

申请号：US720060

申请日：1996-09-27

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

公开(公告)号：US5959894A

公开(公告)日：1999-09-28

申请号：US98747

申请日：1998-06-17

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.