发明授权
- 专利标题: Apparatus and method for an address generation circuit
- 专利标题(中): 地址生成电路的装置和方法
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申请号: US10956164申请日: 2004-09-30
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公开(公告)号: US07380099B2公开(公告)日: 2008-05-27
- 发明人: Sanu K. Mathew , Mark A. Anders , Sarvesh H. Kulkarni , Ram Krishnamurthy
- 申请人: Sanu K. Mathew , Mark A. Anders , Sarvesh H. Kulkarni , Ram Krishnamurthy
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.
公开/授权文献
- US20060069901A1 Apparatus and method for an address generation circuit 公开/授权日:2006-03-30