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公开(公告)号：US07380099B2
公开(公告)日：2008-05-27
申请号：US10956164
申请日：2004-09-30
IPC分类号： G06F12/00
摘要： A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.
摘要翻译： 一种用于地址产生电路的方法和装置。 在一个实施例中，该方法包括计算由多个逻辑地址分量形成的传播信号和生成信号的预定位数的至少一组的进位。 一旦计算了进位，则为逻辑0进位和逻辑1进位产生多个条件和。 随后，从多个条件和中选出一个和，以在第二阶段中的第一阶段的逻辑地址分量和有效地址的第二部分中形成有效地址的第一部分。 在一个实施例中，根据一个实施例，使用产生四分之一载波的完全动态的高性能稀疏树加法器电路来形成地址生成电路。 描述和要求保护其他实施例。
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公开(公告)号：US20120248546A1
公开(公告)日：2012-10-04
申请号：US13077681
申请日：2011-03-31
申请人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
发明人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , H01L21/44 , H01L27/0207 , H01L27/0629 , H01L27/11206 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
摘要翻译： 描述了形成和使用微电子结构的方法。 实施例包括在金属熔丝栅极和PMOS器件之间形成二极管，其中二极管设置在金属熔丝栅极的触点和PMOS器件的触点之间，并且其中二极管将金属熔丝栅极的触点耦合到 PMOS器件的接触。
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公开(公告)号：US08618613B2
公开(公告)日：2013-12-31
申请号：US13077681
申请日：2011-03-31
申请人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
发明人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
CPC分类号： H01L23/5252 , H01L21/44 , H01L27/0207 , H01L27/0629 , H01L27/11206 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
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公开(公告)号：US08395923B2
公开(公告)日：2013-03-12
申请号：US12639446
申请日：2009-12-16
申请人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
发明人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
摘要： Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.
摘要翻译： 公开了用于有效实现诸如PROM，OTPROM和其它这样的可编程非易失性存储器的可编程存储器阵列电路架构的技术和电路。 电路采用反熔丝方案，其包括存储位单元阵列，每个存储器单元包含程序设备和配置有电流路径隔离阱并用于存储存储单元状态的反熔丝元件。 可以与列/行选择电路，功率选择器电路和/或读出电路结合使用的位单元配置允许高密度存储器阵列电路设计和布局。
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公开(公告)号：US20140103448A1
公开(公告)日：2014-04-17
申请号：US14134097
申请日：2013-12-19
申请人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
发明人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , H01L21/44 , H01L27/0207 , H01L27/0629 , H01L27/11206 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
摘要翻译： 描述了形成和使用微电子结构的方法。 实施例包括在金属熔丝栅极和PMOS器件之间形成二极管，其中二极管设置在金属熔丝栅极的触点和PMOS器件的触点之间，并且其中二极管将金属熔丝栅极的触点耦合到 PMOS器件的接触。
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公开(公告)号：US20100165699A1
公开(公告)日：2010-07-01
申请号：US12639446
申请日：2009-12-16
申请人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
发明人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
摘要： Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.
摘要翻译： 公开了用于有效实现诸如PROM，OTPROM和其它这样的可编程非易失性存储器的可编程存储器阵列电路架构的技术和电路。 电路采用反熔丝方案，其包括存储位单元阵列，每个存储器单元包含程序设备和配置有电流路径隔离阱并用于存储存储单元状态的反熔丝元件。 可以与列/行选择电路，功率选择器电路和/或读出电路结合使用的位单元配置允许高密度存储器阵列电路设计和布局。
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