Invention Grant
- Patent Title: Semiconductor processing patterning methods
- Patent Title (中): 半导体加工图案化方法
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Application No.: US10609311Application Date: 2003-06-26
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Publication No.: US07384727B2Publication Date: 2008-06-10
- Inventor: Donald L. Yates
- Applicant: Donald L. Yates
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: G03F7/26
- IPC: G03F7/26
Abstract:
The invention includes semiconductor processing patterning methods and semiconductor constructions. A semiconductor processing patterning method includes forming a second composition resist layer over a different first composition resist layer. Overlapping portions of the first and second composition resist layers are exposed to actinic energy effective to change solubility of the exposed portions versus the unexposed portions of each of the first and second composition resist layers in a developer solution. The first and second composition resist layers are developed with the developer solution under conditions effective to remove the exposed portions of the first composition resist layer at a faster rate than removing the exposed portions of the second composition resist layer. Additional aspects and implementations are contemplated.
Public/Granted literature
- US20040265746A1 Semiconductor processing patterning methods and constructions Public/Granted day:2004-12-30
Information query
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