Invention Grant
US07394694B2 Flash memory device with NAND architecture with reduced capacitive coupling effect
有权
具有NAND架构的闪存器件具有降低的电容耦合效应
- Patent Title: Flash memory device with NAND architecture with reduced capacitive coupling effect
- Patent Title (中): 具有NAND架构的闪存器件具有降低的电容耦合效应
-
Application No.: US11445491Application Date: 2006-05-31
-
Publication No.: US07394694B2Publication Date: 2008-07-01
- Inventor: Rino Micheloni , Roberto Ravasio , Ilaria Motta
- Applicant: Rino Micheloni , Roberto Ravasio , Ilaria Motta
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Seed IP Law Group PLLC
- Agent Lisa K. Jorgenson; Robert Iannucci
- Priority: EP05104742 20050601
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.
Public/Granted literature
- US20060285387A1 Flash memory device with NAND architecture with reduced capacitive coupling effect Public/Granted day:2006-12-21
Information query