公开(公告)号：US07221602B2

公开(公告)日：2007-05-22

申请号：US10735250

申请日：2003-12-12

申请人： Rino Micheloni ,  Roberto Ravasio

发明人： Rino Micheloni ,  Roberto Ravasio

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G06F13/4243 ,  G11C7/04 ,  G11C7/1063 ,  G11C7/22 ,  G11C16/32

摘要： A memory system comprising a semiconductor memory for storing digital data, said memory being connectable to a control device in order to receive an address signal and to make data selected through the output-available address signal. The system is characterised in that it comprises a generating circuit for activating a wait signal to be forwarded to the control device during reading operations in such a way as to indicate the non-availability of the data to be read. The generating circuit is such to deactivate the wait signal, in such a way as to indicate the availability of the data to be read, following a waiting time interval correlated with an effective access time for said memory.

摘要翻译： 一种存储器系统，包括用于存储数字数据的半导体存储器，所述存储器可连接到控制装置，以便接收地址信号并且通过输出可用地址信号选择数据。 该系统的特征在于，其包括用于在读取操作期间激活等待信号以发送到控制设备的发生电路，以便指示要读取的数据的不可用性。 发生电路是这样的，以等待信号去激活，以便在与所述存储器的有效访问时间相关的等待时间间隔之后，指示待读取的数据的可用性。

公开(公告)号：US20070030735A1

公开(公告)日：2007-02-08

申请号：US11495874

申请日：2006-07-28

申请人： Luca Crippa ,  Chiara Missiroli ,  Roberto Ravasio ,  Rino Micheloni ,  Angelo Bovino

发明人： Luca Crippa ,  Chiara Missiroli ,  Roberto Ravasio ,  Rino Micheloni ,  Angelo Bovino

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

摘要： A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell. The enabling means includes reading means for retrieving the existing data value, means for receiving an indication of the target data value, combining means for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication. Conditioning means in the combining means condition a potential of the coupling line based on the existing data value and the modified indication so as to cause the coupling line to take the program enabling potential or the program inhibition potential.

摘要翻译： 一种用于电可编程存储器的页面缓冲器，包括至少一个读/程序单元，其具有可操作地与至少一个所述位线相关联的耦合线，并且适于至少临时存储从或写入到 存储在所选存储单元组的存储单元中的第一或第二存储器页。 读/程序单元包括启用装置，用于通过使耦合线在程序使能电位和程序禁止电位之间采取一种方式来有选择地启用所选择的存储单元的编程状态的改变， 所选存储单元的第一组数据位和已存储在所选存储单元的第二组数据位中的现有数据值。 启用装置包括用于检索现有数据值的读取装置，用于接收目标数据值的指示的装置，用于将接收的目标数据值与所检索的现有数据值组合的组合装置，从而修改目标数据值的所述指示，从而 以获得修改的指示。 组合装置中的调节装置基于现有数据值和修改的指示来条件耦合线的电位，以使耦合线采取程序使能电位或程序禁止电位。

公开(公告)号：US20060059406A1

公开(公告)日：2006-03-16

申请号：US11221584

申请日：2005-09-08

申请人： Rino Micheloni ,  Roberto Ravasio ,  Angelo Bovino ,  Vincenzo Altieri

发明人： Rino Micheloni ,  Roberto Ravasio ,  Angelo Bovino ,  Vincenzo Altieri

IPC分类号： G11C29/00

CPC分类号： G06F11/1048

摘要： A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

公开(公告)号：US20110167318A1

公开(公告)日：2011-07-07

申请号：US13047678

申请日：2011-03-14

申请人： Alessia Marelli ,  Valeria Intini ,  Roberto Ravasio ,  Rino Micheloni

发明人： Alessia Marelli ,  Valeria Intini ,  Roberto Ravasio ,  Rino Micheloni

IPC分类号： G06F11/10

CPC分类号： G06F11/1076 ,  G06F11/1068 ,  G06F11/141 ,  G11B20/18

摘要： A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS-1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated, On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).

摘要翻译： 具有纠错编码的存储器件的读取方法设想的步骤是：执行多个存储器位置（A0，A1，...，ALS-1）的第一读取以产生第一恢复串（S1） ，并且使用第一恢复串执行第一解码尝试（S1）。 当第一解码尝试失败时，至少读取一次存储器位置，并且生成至少一个第二恢复串（S2-SN）。基于第一恢复串（S1）与第二恢复串 恢复字符串（S2-SN），生成修改字符串（SM），其中存在擦除（X），并且使用修改字符串（SM）执行至少一个第二解码尝试。

公开(公告)号：US20110167206A1

公开(公告)日：2011-07-07

申请号：US13048760

申请日：2011-03-15

申请人： Angelo Bovino ,  Roberto Ravasio ,  Rino Micheloni

发明人： Angelo Bovino ,  Roberto Ravasio ,  Rino Micheloni

IPC分类号： G06F12/02

CPC分类号： G11C11/5621 ,  G11C16/20

摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.

摘要翻译： 多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能的算法。 在测试期间识别存储器件的操作参数的最佳配置通过允许将配置位一次性处理成算法友好的数据来简化，该数据存储在嵌入式辅助随机存取存储器中，每次上电时 存储设备。 这通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来完成。

公开(公告)号：US07394694B2

公开(公告)日：2008-07-01

申请号：US11445491

申请日：2006-05-31

申请人： Rino Micheloni ,  Roberto Ravasio ,  Ilaria Motta

发明人： Rino Micheloni ,  Roberto Ravasio ,  Ilaria Motta

IPC分类号： G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/3409

摘要： A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.

摘要翻译： NAND闪速存储器件包括每个具有阈值电压的存储器单元矩阵。 矩阵包括单独的可擦除扇区，并且被布置成多行和列，其中每列的单元被排列成串联连接的多个单元格单元。 存储器件包括擦除所选扇区的单元的逻辑，以及恢复已擦除单元的阈值电压的恢复逻辑。 恢复逻辑依次作用于扇区的多个块中的每个块，每个块包括一个或多个单元的组。 恢复逻辑相对于超过读取参考值的限制值读取每个组，仅对至少一个单元的阈值电压没有达到极限值的每个组进行编程，并且响应于达到极限值而停止恢复 至少一组这些组。

公开(公告)号：US07382660B2

公开(公告)日：2008-06-03

申请号：US11458904

申请日：2006-07-20

申请人： Angelo Bovino ,  Vincenzo Altieri ,  Roberto Ravasio ,  Rino Micheloni ,  Mario De Matteis

发明人： Angelo Bovino ,  Vincenzo Altieri ,  Roberto Ravasio ,  Rino Micheloni ,  Mario De Matteis

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C2211/5641

摘要： Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.

摘要翻译： 多级编程允许通过从第二位单独编程第一位来在选定单元中写入第一位和第二位。 第一位的编程确定从第一阈值电平转换到第二阈值电平。 第二位的编程需要初步读取以检测第一位是否已被修改，如果第一位已被修改并执行第二写入步骤，执行第一写入步骤以使单元进入第三阈值电压，以使所选择的 如果第一位未被修改，则将单元转换为不同于第三阈值电平的第四阈值电压。 为了增加读取和编程的可靠性，在第二部分的初步读取期间，读取结果被迫对应于第一阈值水平。

公开(公告)号：US20070030730A1

公开(公告)日：2007-02-08

申请号：US11495886

申请日：2006-07-28

申请人： Angelo Bovino ,  Rino Micheloni ,  Roberto Ravasio

发明人： Angelo Bovino ,  Rino Micheloni ,  Roberto Ravasio

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

摘要： A non-volatile memory device is proposed. The non-volatile memory device includes a plurality of memory cells each one having a programmable threshold voltage, and means for reading a set of selected memory cells with respect to a plurality of reference voltages, for each selected memory cell the means for reading including means for charging a reading node associated with the selected memory cell with a charging voltage, means for biasing the selected memory cell with a biasing voltage, means for connecting the charged reading node with the biased selected memory cell, and means for sensing a voltage at the reading node after a predefined delay from the connection, for at least a first one of the reference voltages the biasing voltage being a first biasing voltage equal to the first reference voltage and the delay being a common first delay, wherein for at least a second one of the reference voltages the biasing voltage is a second biasing voltage different from the second reference voltage, and the delay is a second delay different from the first delay.

摘要翻译： 提出了一种非易失性存储器件。 该非易失性存储器件包括多个具有可编程阈值电压的存储单元，以及用于针对每个所选择的存储器单元读取相对于多个参考电压的一组所选存储单元的装置，所述读取装置包括装置 用于利用充电电压对与所选择的存储器单元相关联的读取节点进行充电，用于利用偏置电压偏置所选择的存储单元的装置，用于将所述充电的读取节点与所偏置的选择的存储单元相连接的装置，以及用于感测所述存储单元 在来自所述连接的预定义延迟之后的读取节点，对于所述参考电压中的至少第一参考电压，所述偏置电压是等于所述第一参考电压的第一偏置电压，并且所述延迟是公共的第一延迟，其中对于至少第二个 的参考电压，偏置电压是与第二参考电压不同的第二偏置电压，并且延迟是第二延迟di 与第一次延迟不同。

公开(公告)号：US07035142B2

公开(公告)日：2006-04-25

申请号：US10748696

申请日：2003-12-30

申请人： Osama Khouri ,  Roberto Ravasio ,  Rino Micheloni ,  Giovanni Campardo

发明人： Osama Khouri ,  Roberto Ravasio ,  Rino Micheloni ,  Giovanni Campardo

IPC分类号： G11C16/06

CPC分类号： G11C29/76

摘要： The device includes a circuit for sector remapping having a CAM (Content Addressable Memory) unit, associated to and in data communication with a multiplexer unit. The CAM unit detects that a sector is defective, it provides the pre-programmed address of a replacing sector and it activates the multiplexer which performs the replacement. The defective sectors and the corresponding locations of the address map are therefore advantageously positioned to the rear to the addressing area. The addressing area is consequently continuous, thus allowing the information to be easily stored and retrieved.

摘要翻译： 该设备包括用于扇区重新映射的电路，其具有与多路复用器单元相关联并且与多路复用器单元进行数据通信的CAM（内容可寻址存储器）单元。 CAM单元检测到扇区有故障，它提供替换扇区的预编程地址，并激活执行替换的多路复用器。 因此，有缺陷的扇区和地址图的相应位置有利地位于寻址区的后方。 因此，寻址区域是连续的，从而可以容易地存储和检索信息。

公开(公告)号：US07031193B2

公开(公告)日：2006-04-18

申请号：US10729875

申请日：2003-12-05

申请人： Rino Micheloni ,  Roberto Ravasio ,  Salvatrice Scommegna

发明人： Rino Micheloni ,  Roberto Ravasio ,  Salvatrice Scommegna

IPC分类号： G11C16/06

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A device and method for programming an electrically programmable memory accesses a group of memory cells (MC1–MCk) of the memory to ascertain a programming state thereof (401,407;503,509a,513a); applies a programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state (405;507a,509c,513c); and repeats the steps of accessing and applying for the memory cells in the group whose programming state is not ascertained (411;509b,513b). After the programming state of a prescribed number of memory cells in the group has been ascertained, the memory cells in the group are accessed again and the programming state of the memory cells whose programming state was previously ascertained is re-ascertained (413,415;515). At least one additional programming pulse is applied to those memory cells in the group whose programming state is not re-ascertained (405;507a,509c,513c). The method guarantees that the programming state of the memory cells is ascertained in conditions that closely resembles, or are substantially identical, to the conditions in which the memory cells will be accessed in a standard read.

摘要翻译： 用于编程电可编程存储器的装置和方法访问存储器的一组存储器单元（MC 1 -MC k）以确定其编程状态（401,407; 503,509a，513a）; 对编程状态未被确定的组中的那些存储单元施加编程脉冲以对应于期望的编程状态（405; 507a，509c，513c）; 并重复访问和应用编程状态未确定的组中的存储单元的步骤（411; 509b，513b）。 在已经确定组中规定数量的存储单元的编程状态之后，再次访问组中的存储单元，并且重新确定编程状态被预先确定的存储单元的编程状态（413,415; 515） 。 至少一个附加的编程脉冲被施加到编程状态未重新确定的组中的那些存储器单元（405; 507a，509c，513c）。 该方法确保在与标准读取存储器单元访问的条件非常相似或基本相同的条件下确定存储器单元的编程状态。