公开(公告)号：US07394694B2

公开(公告)日：2008-07-01

申请号：US11445491

申请日：2006-05-31

申请人： Rino Micheloni ,  Roberto Ravasio ,  Ilaria Motta

发明人： Rino Micheloni ,  Roberto Ravasio ,  Ilaria Motta

IPC分类号： G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/3409

摘要： A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.

摘要翻译： NAND闪速存储器件包括每个具有阈值电压的存储器单元矩阵。 矩阵包括单独的可擦除扇区，并且被布置成多行和列，其中每列的单元被排列成串联连接的多个单元格单元。 存储器件包括擦除所选扇区的单元的逻辑，以及恢复已擦除单元的阈值电压的恢复逻辑。 恢复逻辑依次作用于扇区的多个块中的每个块，每个块包括一个或多个单元的组。 恢复逻辑相对于超过读取参考值的限制值读取每个组，仅对至少一个单元的阈值电压没有达到极限值的每个组进行编程，并且响应于达到极限值而停止恢复 至少一组这些组。

公开(公告)号：US07221602B2

公开(公告)日：2007-05-22

申请号：US10735250

申请日：2003-12-12

申请人： Rino Micheloni ,  Roberto Ravasio

发明人： Rino Micheloni ,  Roberto Ravasio

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G06F13/4243 ,  G11C7/04 ,  G11C7/1063 ,  G11C7/22 ,  G11C16/32

摘要： A memory system comprising a semiconductor memory for storing digital data, said memory being connectable to a control device in order to receive an address signal and to make data selected through the output-available address signal. The system is characterised in that it comprises a generating circuit for activating a wait signal to be forwarded to the control device during reading operations in such a way as to indicate the non-availability of the data to be read. The generating circuit is such to deactivate the wait signal, in such a way as to indicate the availability of the data to be read, following a waiting time interval correlated with an effective access time for said memory.

摘要翻译： 一种存储器系统，包括用于存储数字数据的半导体存储器，所述存储器可连接到控制装置，以便接收地址信号并且通过输出可用地址信号选择数据。 该系统的特征在于，其包括用于在读取操作期间激活等待信号以发送到控制设备的发生电路，以便指示要读取的数据的不可用性。 发生电路是这样的，以等待信号去激活，以便在与所述存储器的有效访问时间相关的等待时间间隔之后，指示待读取的数据的可用性。

公开(公告)号：US20070030735A1

公开(公告)日：2007-02-08

申请号：US11495874

申请日：2006-07-28

申请人： Luca Crippa ,  Chiara Missiroli ,  Roberto Ravasio ,  Rino Micheloni ,  Angelo Bovino

发明人： Luca Crippa ,  Chiara Missiroli ,  Roberto Ravasio ,  Rino Micheloni ,  Angelo Bovino

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

摘要： A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell. The enabling means includes reading means for retrieving the existing data value, means for receiving an indication of the target data value, combining means for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication. Conditioning means in the combining means condition a potential of the coupling line based on the existing data value and the modified indication so as to cause the coupling line to take the program enabling potential or the program inhibition potential.

摘要翻译： 一种用于电可编程存储器的页面缓冲器，包括至少一个读/程序单元，其具有可操作地与至少一个所述位线相关联的耦合线，并且适于至少临时存储从或写入到 存储在所选存储单元组的存储单元中的第一或第二存储器页。 读/程序单元包括启用装置，用于通过使耦合线在程序使能电位和程序禁止电位之间采取一种方式来有选择地启用所选择的存储单元的编程状态的改变， 所选存储单元的第一组数据位和已存储在所选存储单元的第二组数据位中的现有数据值。 启用装置包括用于检索现有数据值的读取装置，用于接收目标数据值的指示的装置，用于将接收的目标数据值与所检索的现有数据值组合的组合装置，从而修改目标数据值的所述指示，从而 以获得修改的指示。 组合装置中的调节装置基于现有数据值和修改的指示来条件耦合线的电位，以使耦合线采取程序使能电位或程序禁止电位。

公开(公告)号：US20060059406A1

公开(公告)日：2006-03-16

申请号：US11221584

申请日：2005-09-08

申请人： Rino Micheloni ,  Roberto Ravasio ,  Angelo Bovino ,  Vincenzo Altieri

发明人： Rino Micheloni ,  Roberto Ravasio ,  Angelo Bovino ,  Vincenzo Altieri

IPC分类号： G11C29/00

CPC分类号： G06F11/1048

摘要： A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

公开(公告)号：US07730357B2

公开(公告)日：2010-06-01

申请号：US10805182

申请日：2004-03-19

申请人： Rino Micheloni ,  Roberto Ravasio

发明人： Rino Micheloni ,  Roberto Ravasio

IPC分类号： G06F11/00

CPC分类号： G06F11/1068 ,  G06F11/1048

摘要： An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.

摘要翻译： 本发明的实施例涉及至少包括非易失性存储器和自动存储错误校正器的集成存储器系统，并且其中存储器通过接口总线连接到控制器。 有利地，该系统在存储器电路装置中包括功能上独立的，每个都负责校正预定的存储错误; 所述装置中的至少一个产生要求校正在存储器外部的信号。

公开(公告)号：US07719894B2

公开(公告)日：2010-05-18

申请号：US11828716

申请日：2007-07-26

申请人： Luca Crippa ,  Roberto Ravasio ,  Rino Micheloni

发明人： Luca Crippa ,  Roberto Ravasio ,  Rino Micheloni

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C7/18 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

摘要： The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.

摘要翻译： 可以利用NAND存储器件的两个相邻位线之间的电容耦合来升高不被编程的位线的电压，以便禁止对它们的编程操作。 包括不被编程的单元的偶数（奇数）位线用第一电压偏置，以阻止它们被编程，而包括要编程的单元的偶数（奇数）位线接地。 相邻的奇数（偶数）位线在电源电压或辅助电压处偏置，用于将偶数（奇数）位线的偏置电压升高到电源电压以上。 由于相邻位线之间的相关寄生耦合电容，包括不编程单元的偶数（奇数）位线的偏置电压会升高。

公开(公告)号：US07068540B2

公开(公告)日：2006-06-27

申请号：US10729829

申请日：2003-12-05

申请人： Rino Micheloni ,  Roberto Ravasio

发明人： Rino Micheloni ,  Roberto Ravasio

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454

摘要： A device and method for programming an electrically programmable memory applies at least one first programming pulse to a group of memory cells (MC1–MCk) of the memory, accesses the memory cells of the group to ascertain a programming state thereof, and applies at least one second programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state. A voltage applied to a control electrode of the memory cells is varied between the at least one first programming pulse and the at least one second programming pulse according to a forecasted change in biasing conditions of the memory cells in the group between said at least one first and at least one second programming pulses. Undesired over-programming of the memory cells is thus avoided.

摘要翻译： 用于编程电可编程存储器的装置和方法将至少一个第一编程脉冲施加到存储器的一组存储器单元（MC 1 -MC k），访问该组的存储器单元以确定其编程状态，并应用于 至少一秒编程脉冲到组中编程状态未被确定以对应于期望的编程状态的那些存储器单元。 根据在所述至少一个第一编程脉冲和所述至少一个第二编程脉冲之间的所述组中的存储器单元的偏置条件的预测变化，施加到所述存储器单元的控制电极的电压在所述至少一个第一编程脉冲和所述至少一个第二编程脉冲之间变化 和至少一个第二编程脉冲。 因此避免了对存储器单元的不期望​​的过度编程。

公开(公告)号：US07017099B2

公开(公告)日：2006-03-21

申请号：US10159782

申请日：2002-05-30

申请人： Rino Micheloni ,  Massimiliano Picca ,  Roberto Ravasio ,  Stefano Zanardi

发明人： Rino Micheloni ,  Massimiliano Picca ,  Roberto Ravasio ,  Stefano Zanardi

IPC分类号： H03M13/00

CPC分类号： G06F11/1072 ,  G11C2211/5641

摘要： A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

公开(公告)号：US20110167318A1

公开(公告)日：2011-07-07

申请号：US13047678

申请日：2011-03-14

申请人： Alessia Marelli ,  Valeria Intini ,  Roberto Ravasio ,  Rino Micheloni

发明人： Alessia Marelli ,  Valeria Intini ,  Roberto Ravasio ,  Rino Micheloni

IPC分类号： G06F11/10

CPC分类号： G06F11/1076 ,  G06F11/1068 ,  G06F11/141 ,  G11B20/18

摘要： A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS-1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated, On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).

摘要翻译： 具有纠错编码的存储器件的读取方法设想的步骤是：执行多个存储器位置（A0，A1，...，ALS-1）的第一读取以产生第一恢复串（S1） ，并且使用第一恢复串执行第一解码尝试（S1）。 当第一解码尝试失败时，至少读取一次存储器位置，并且生成至少一个第二恢复串（S2-SN）。基于第一恢复串（S1）与第二恢复串 恢复字符串（S2-SN），生成修改字符串（SM），其中存在擦除（X），并且使用修改字符串（SM）执行至少一个第二解码尝试。

公开(公告)号：US20110167206A1

公开(公告)日：2011-07-07

申请号：US13048760

申请日：2011-03-15

申请人： Angelo Bovino ,  Roberto Ravasio ,  Rino Micheloni

发明人： Angelo Bovino ,  Roberto Ravasio ,  Rino Micheloni

IPC分类号： G06F12/02

CPC分类号： G11C11/5621 ,  G11C16/20

摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.

摘要翻译： 多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能的算法。 在测试期间识别存储器件的操作参数的最佳配置通过允许将配置位一次性处理成算法友好的数据来简化，该数据存储在嵌入式辅助随机存取存储器中，每次上电时 存储设备。 这通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来完成。