发明授权
US07397259B1 Method and apparatus for statistical CMOS device characterization
失效
用于统计CMOS器件表征的方法和装置
- 专利标题: Method and apparatus for statistical CMOS device characterization
- 专利标题(中): 用于统计CMOS器件表征的方法和装置
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申请号: US11736146申请日: 2007-04-17
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公开(公告)号: US07397259B1公开(公告)日: 2008-07-08
- 发明人: Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
- 申请人: Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Casimer K. Salys; Jack V. Musgrove
- 主分类号: G01R31/26
- IPC分类号: G01R31/26 ; G01R33/00 ; G01R31/02
摘要:
A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columnns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.